[PATCH 3/3] drm/amd/amdgpu: Add bank selection for MMIO debugfs (v3)
Nicolai Hähnle
nhaehnle at gmail.com
Wed Jun 29 14:20:25 UTC 2016
Patch 1 & 3 are
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Patch 2 looks mostly fine to me, too, but I'm not sure about the
vmalloc/vfree vs. kmalloc/kfree.
Cheers,
Nicolai
On 29.06.2016 15:56, Tom St Denis wrote:
> (v2) Added INSTANCE selector
> (v3) Changed order of bank selectors
>
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 35 +++++++++++++++++++++++++++---
> 1 file changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7f08ac02f9de..4a8f66c5ff43 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2244,20 +2244,43 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
> struct amdgpu_device *adev = f->f_inode->i_private;
> ssize_t result = 0;
> int r;
> + bool use_bank;
> + unsigned instance_bank, sh_bank, se_bank;
>
> if (size & 0x3 || *pos & 0x3)
> return -EINVAL;
>
> + if (*pos & (1ULL << 62)) {
> + se_bank = (*pos >> 24) & 0x3FF;
> + sh_bank = (*pos >> 34) & 0x3FF;
> + instance_bank = (*pos >> 44) & 0x3FF;
> + use_bank = 1;
> + *pos &= 0xFFFFFF;
> + } else {
> + use_bank = 0;
> + }
> +
> + if (use_bank) {
> + if (sh_bank >= adev->gfx.config.max_sh_per_se ||
> + se_bank >= adev->gfx.config.max_shader_engines)
> + return -EINVAL;
> + mutex_lock(&adev->grbm_idx_mutex);
> + amdgpu_gfx_select_se_sh(adev, se_bank,
> + sh_bank, instance_bank);
> + }
> +
> while (size) {
> uint32_t value;
>
> if (*pos > adev->rmmio_size)
> - return result;
> + goto end;
>
> value = RREG32(*pos >> 2);
> r = put_user(value, (uint32_t *)buf);
> - if (r)
> - return r;
> + if (r) {
> + result = r;
> + goto end;
> + }
>
> result += 4;
> buf += 4;
> @@ -2265,6 +2288,12 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
> size -= 4;
> }
>
> +end:
> + if (use_bank) {
> + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
> + mutex_unlock(&adev->grbm_idx_mutex);
> + }
> +
> return result;
> }
>
>
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