[PATCH] drm/amdgpu: refine uvd_4.2 clock gate sequence.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, November 04, 2016 9:11 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: refine uvd_4.2 clock gate sequence.
> 
> 1. partial revert commit 91db308d6e96.
>    not set uvd bypass mode.
> 2. enable uvd cg before initialize uvd.
> 3. set uvd clock to default value 100MHz.
> 
> Change-Id: I7d1f2ede425c6b97bf4439f445a06d2cff391d61

Missing signed-off-by.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/ci_dpm.c   |  8 -------
>  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 40 ++++++++---------------------
> ------
>  2 files changed, 9 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index e91558c..538e5d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -4197,11 +4197,6 @@ static int ci_update_uvd_dpm(struct
> amdgpu_device *adev, bool gate)
> 
>  	if (!gate) {
>  		/* turn the clocks on when decoding */
> -		ret = amdgpu_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> -
> AMD_CG_STATE_UNGATE);
> -		if (ret)
> -			return ret;
> -
>  		if (pi->caps_uvd_dpm ||
>  		    (adev-
> >pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
>  			pi->smc_state_table.UvdBootLevel = 0;
> @@ -4218,9 +4213,6 @@ static int ci_update_uvd_dpm(struct
> amdgpu_device *adev, bool gate)
>  		ret = ci_enable_uvd_dpm(adev, false);
>  		if (ret)
>  			return ret;
> -
> -		ret = amdgpu_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> -						    AMD_CG_STATE_GATE);
>  	}
> 
>  	return ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 6eed65c..fd971fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -45,7 +45,8 @@ static void uvd_v4_2_set_ring_funcs(struct
> amdgpu_device *adev);
>  static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
>  static int uvd_v4_2_start(struct amdgpu_device *adev);
>  static void uvd_v4_2_stop(struct amdgpu_device *adev);
> -
> +static int uvd_v4_2_set_clockgating_state(void *handle,
> +				enum amd_clockgating_state state);
>  /**
>   * uvd_v4_2_ring_get_rptr - get read pointer
>   *
> @@ -155,9 +156,9 @@ static int uvd_v4_2_hw_init(void *handle)
>  	uint32_t tmp;
>  	int r;
> 
> -	/* raise clocks while booting up the VCPU */
> -	amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
> -
> +	uvd_v4_2_init_cg(adev);
> +	uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE);
> +	amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
>  	r = uvd_v4_2_start(adev);
>  	if (r)
>  		goto done;
> @@ -197,8 +198,6 @@ static int uvd_v4_2_hw_init(void *handle)
>  	amdgpu_ring_commit(ring);
> 
>  done:
> -	/* lower clocks again */
> -	amdgpu_asic_set_uvd_clocks(adev, 0, 0);
> 
>  	if (!r)
>  		DRM_INFO("UVD initialized successfully.\n");
> @@ -275,9 +274,6 @@ static int uvd_v4_2_start(struct amdgpu_device
> *adev)
> 
>  	uvd_v4_2_mc_resume(adev);
> 
> -	/* disable clock gating */
> -	WREG32(mmUVD_CGC_GATE, 0);
> -
>  	/* disable interupt */
>  	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
> 
> @@ -583,8 +579,6 @@ static void uvd_v4_2_mc_resume(struct
> amdgpu_device *adev)
>  	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev-
> >gfx.config.gb_addr_config);
>  	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev-
> >gfx.config.gb_addr_config);
>  	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev-
> >gfx.config.gb_addr_config);
> -
> -	uvd_v4_2_init_cg(adev);
>  }
> 
>  static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
> @@ -594,7 +588,7 @@ static void uvd_v4_2_enable_mgcg(struct
> amdgpu_device *adev,
> 
>  	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
> {
>  		data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
> -		data = 0xfff;
> +		data |= 0xfff;
>  		WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
> 
>  		orig = data = RREG32(mmUVD_CGC_CTRL);
> @@ -701,34 +695,18 @@ static int uvd_v4_2_process_interrupt(struct
> amdgpu_device *adev,
>  	return 0;
>  }
> 
> -static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool
> enable)
> -{
> -	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
> -
> -	if (enable)
> -		tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
> -			GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
> -	else
> -		tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
> -			 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
> -
> -	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
> -}
> -
>  static int uvd_v4_2_set_clockgating_state(void *handle,
>  					  enum amd_clockgating_state state)
>  {
>  	bool gate = false;
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> -	if (state == AMD_CG_STATE_GATE)
> -		gate = true;
> -
> -	uvd_v5_0_set_bypass_mode(adev, gate);
> -
>  	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
>  		return 0;
> 
> +	if (state == AMD_CG_STATE_GATE)
> +		gate = true;
> +
>  	uvd_v4_2_enable_mgcg(adev, gate);
> 
>  	return 0;
> --
> 1.9.1
> 
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