[PATCH 13/76] drm/amd/dal: DCC support
Harry Wentland
harry.wentland at amd.com
Mon Nov 21 23:00:33 UTC 2016
From: Tony Cheng <tony.cheng at amd.com>
Signed-off-by: Tony Cheng <tony.cheng at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
drivers/gpu/drm/amd/dal/dc/dc.h | 43 ++++++++++++++++---
drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 48 ++++++++++++++++++++--
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 2 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h | 2 +-
7 files changed, 87 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 2a6117ae85e3..0451b610b3e2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -50,21 +50,52 @@ struct dc_caps {
uint32_t i2c_speed_in_khz;
};
+
+struct dc_dcc_surface_param {
+ enum surface_pixel_format format;
+ struct dc_size surface_size;
+ enum dc_scan_direction scan;
+};
+
+struct dc_dcc_setting {
+ unsigned int max_compressed_blk_size;
+ unsigned int max_uncompressed_blk_size;
+ bool independent_64b_blks;
+};
+
+struct dc_surface_dcc_cap {
+ bool capable;
+ bool const_color_support;
+
+ union {
+ struct {
+ struct dc_dcc_setting rgb;
+ } grph;
+
+ struct {
+ struct dc_dcc_setting luma;
+ struct dc_dcc_setting chroma;
+ } video;
+ };
+};
+
/* Forward declaration*/
struct dc;
struct dc_surface;
struct validate_context;
+struct dc_cap_funcs {
+ int i;
+};
+
struct dc_stream_funcs {
- bool (*adjust_vmin_vmax)(
- struct dc *dc,
+ bool (*adjust_vmin_vmax)(struct dc *dc,
const struct dc_stream **stream,
int num_streams,
int vmin,
int vmax);
- void (*stream_update_scaling)(
- const struct dc *dc,
+ void (*stream_update_scaling)(const struct dc *dc,
const struct dc_stream *dc_stream,
const struct rect *src,
const struct rect *dst);
@@ -106,10 +137,12 @@ struct dc_config {
struct dc_debug {
bool surface_visual_confirm;
bool disable_stutter;
+ bool disable_dcc;
};
struct dc {
struct dc_caps caps;
+ struct dc_cap_funcs cap_funcs;
struct dc_stream_funcs stream_funcs;
struct dc_link_funcs link_funcs;
struct dc_config config;
@@ -189,8 +222,8 @@ struct dc_surface {
union plane_size plane_size;
union dc_tiling_info tiling_info;
+ struct dc_plane_dcc_param dcc;
enum dc_color_space color_space;
- bool compressed;
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
index 246110201c10..29e65a42930c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
@@ -65,25 +65,40 @@ struct dc_plane_address {
union {
struct{
PHYSICAL_ADDRESS_LOC addr;
- PHYSICAL_ADDRESS_LOC meta;
+ PHYSICAL_ADDRESS_LOC meta_addr;
+ union large_integer dcc_const_color;
} grph;
/*stereo*/
struct {
PHYSICAL_ADDRESS_LOC left_addr;
+ PHYSICAL_ADDRESS_LOC left_meta_addr;
+ union large_integer left_dcc_const_color;
+
PHYSICAL_ADDRESS_LOC right_addr;
+ PHYSICAL_ADDRESS_LOC right_meta_addr;
+ union large_integer right_dcc_const_color;
+
} grph_stereo;
/*video progressive*/
struct {
- PHYSICAL_ADDRESS_LOC meta_chroma;
- PHYSICAL_ADDRESS_LOC meta_luma;
- PHYSICAL_ADDRESS_LOC chroma_addr;
PHYSICAL_ADDRESS_LOC luma_addr;
+ PHYSICAL_ADDRESS_LOC luma_meta_addr;
+ union large_integer luma_dcc_const_color;
+
+ PHYSICAL_ADDRESS_LOC chroma_addr;
+ PHYSICAL_ADDRESS_LOC chroma_meta_addr;
+ union large_integer chroma_dcc_const_color;
} video_progressive;
};
};
+struct dc_size {
+ uint32_t width;
+ uint32_t height;
+};
+
struct rect {
int x;
int y;
@@ -128,6 +143,25 @@ union plane_size {
} video;
};
+struct dc_plane_dcc_param {
+ bool enable;
+
+ union {
+ struct {
+ uint32_t meta_pitch;
+ bool independent_64b_blks;
+ } grph;
+
+ struct {
+ uint32_t meta_pitch_l;
+ bool independent_64b_blks_l;
+
+ uint32_t meta_pitch_c;
+ bool independent_64b_blks_c;
+ } video;
+ };
+};
+
/*Displayable pixel format in fb*/
enum surface_pixel_format {
SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
@@ -298,6 +332,12 @@ enum dc_rotation_angle {
ROTATION_ANGLE_COUNT
};
+enum dc_scan_direction {
+ SCAN_DIRECTION_UNKNOWN = 0,
+ SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */
+ SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */
+};
+
struct dc_cursor_position {
uint32_t x;
uint32_t y;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 1da40156cb9a..123881f426fe 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1606,7 +1606,7 @@ static void set_plane_config(
&surface->public.tiling_info,
&surface->public.plane_size,
surface->public.rotation,
- false);
+ NULL);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 758884803ef3..3183728ed417 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -525,7 +525,7 @@ bool dce110_mem_input_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed)
+ struct dc_plane_dcc_param *dcc)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
index 4eeca44d20c7..c9e3f5c1fa22 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
@@ -128,7 +128,7 @@ bool dce110_mem_input_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed);
+ struct dc_plane_dcc_param *dcc);
/*
* dce110_mem_input_program_pte_vm
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
index 2af14f7558bd..5376fed66c29 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
@@ -666,7 +666,7 @@ bool dce110_mem_input_v_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed)
+ struct dc_plane_dcc_param *dcc)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
index fd68dc037a83..9ad3b4218cb0 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
@@ -80,7 +80,7 @@ struct mem_input_funcs {
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed);
+ struct dc_plane_dcc_param *dcc);
bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
};
--
2.10.1
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