[PATCH 15/39] drm/amd/dal: drop dce80 transform code
Harry Wentland
harry.wentland at amd.com
Thu Nov 24 02:02:44 UTC 2016
From: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Change-Id: I6165e22617332b9effc8d4aaf00685b3a417f7e0
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 10 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.h | 5 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 1 +
drivers/gpu/drm/amd/dal/dc/dce80/Makefile | 5 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 85 +--
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c | 103 ---
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h | 75 ---
.../amd/dal/dc/dce80/dce80_transform_bit_depth.c | 671 -------------------
.../amd/dal/dc/dce80/dce80_transform_bit_depth.h | 37 --
.../drm/amd/dal/dc/dce80/dce80_transform_gamut.c | 269 --------
.../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c | 737 ---------------------
11 files changed, 44 insertions(+), 1954 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
index 02a29f3cc5d5..4079a64d6958 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
@@ -684,13 +684,12 @@ bool dce110_transform_get_optimal_number_of_taps(
struct scaler_data *scl_data,
const struct scaling_taps *in_taps)
{
- uint32_t pixel_width;
-
+ struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
+ int pixel_width = scl_data->viewport.width;
- if (scl_data->viewport.width > scl_data->recout.width)
+ if (xfm110->prescaler_on &&
+ (scl_data->viewport.width > scl_data->recout.width))
pixel_width = scl_data->recout.width;
- else
- pixel_width = scl_data->viewport.width;
return transform_get_optimal_number_of_taps_helper(
xfm,
@@ -742,6 +741,7 @@ bool dce110_transform_construct(
xfm110->xfm_shift = xfm_shift;
xfm110->xfm_mask = xfm_mask;
+ xfm110->prescaler_on = true;
xfm110->lb_pixel_depth_supported =
LB_PIXEL_DEPTH_18BPP |
LB_PIXEL_DEPTH_24BPP |
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
index d1f53816b4c5..f8f320ff2ee5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
@@ -111,7 +111,6 @@
XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
- XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh), \
XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
@@ -146,7 +145,8 @@
#define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
- XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh)
+ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
+ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
struct dce110_transform_shift {
@@ -336,6 +336,7 @@ struct dce110_transform {
const uint16_t *filter_v_c;
const uint16_t *filter_h_c;
uint32_t lb_pixel_depth_supported;
+ bool prescaler_on;
};
bool dce110_transform_construct(struct dce110_transform *xfm110,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
index 845859d2f102..497694721023 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
@@ -699,6 +699,7 @@ bool dce110_transform_v_construct(
LB_PIXEL_DEPTH_24BPP |
LB_PIXEL_DEPTH_30BPP;
+ xfm110->prescaler_on = true;
xfm110->base.lb_bits_per_entry = LB_BITS_PER_ENTRY;
xfm110->base.lb_total_entries_num = LB_TOTAL_NUMBER_OF_ENTRIES;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/Makefile b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
index 863641ca07a6..fdcac289feec 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
@@ -4,10 +4,9 @@
DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_opp.o \
dce80_opp_formatter.o dce80_opp_regamma.o \
- dce80_timing_generator.o dce80_transform.o dce80_transform_gamut.o \
- dce80_transform_scl.o dce80_opp_csc.o\
+ dce80_timing_generator.o dce80_opp_csc.o\
dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \
- dce80_transform_bit_depth.o dce80_resource.o
+ dce80_resource.o
AMD_DAL_DCE80 = $(addprefix $(AMDDALPATH)/dc/dce80/,$(DCE80))
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index dbdce062e4e9..48dd7c600619 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -41,7 +41,7 @@
#include "dce/dce_stream_encoder.h"
#include "dce80/dce80_mem_input.h"
#include "dce80/dce80_ipp.h"
-#include "dce80/dce80_transform.h"
+#include "dce110/dce110_transform.h"
#include "dce80/dce80_opp.h"
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_clock_source.h"
@@ -183,49 +183,6 @@ static const struct dce110_mem_input_reg_offsets dce80_mi_reg_offsets[] = {
}
};
-static const struct dce80_transform_reg_offsets dce80_xfm_offsets[] = {
-{
- .scl_offset = (mmSCL_CONTROL - mmSCL_CONTROL),
- .crtc_offset = (mmDCFE_MEM_LIGHT_SLEEP_CNTL -
- mmDCFE_MEM_LIGHT_SLEEP_CNTL),
- .dcp_offset = (mmGRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
- .crtc_offset = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL -
- mmDCFE_MEM_LIGHT_SLEEP_CNTL),
- .dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
- .crtc_offset = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL -
- mmDCFE_MEM_LIGHT_SLEEP_CNTL),
- .dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{
- .scl_offset = (mmSCL3_SCL_CONTROL - mmSCL_CONTROL),
- .crtc_offset = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL -
- mmDCFE_MEM_LIGHT_SLEEP_CNTL),
- .dcp_offset = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB3_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{
- .scl_offset = (mmSCL4_SCL_CONTROL - mmSCL_CONTROL),
- .crtc_offset = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL -
- mmDCFE_MEM_LIGHT_SLEEP_CNTL),
- .dcp_offset = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB4_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{
- .scl_offset = (mmSCL5_SCL_CONTROL - mmSCL_CONTROL),
- .crtc_offset = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL -
- mmDCFE_MEM_LIGHT_SLEEP_CNTL),
- .dcp_offset = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB5_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-}
-};
-
static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
{
.dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL),
@@ -255,6 +212,28 @@ static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
+#define transform_regs(id)\
+[id] = {\
+ XFM_COMMON_REG_LIST_DCE_BASE(id)\
+}
+
+static const struct dce110_transform_registers xfm_regs[] = {
+ transform_regs(0),
+ transform_regs(1),
+ transform_regs(2),
+ transform_regs(3),
+ transform_regs(4),
+ transform_regs(5)
+};
+
+static const struct dce110_transform_shift xfm_shift = {
+ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce110_transform_mask xfm_mask = {
+ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
#define aux_regs(id)\
[id] = {\
AUX_REG_LIST(id)\
@@ -519,23 +498,26 @@ static struct mem_input *dce80_mem_input_create(
static void dce80_transform_destroy(struct transform **xfm)
{
- dm_free(TO_DCE80_TRANSFORM(*xfm));
+ dm_free(TO_DCE110_TRANSFORM(*xfm));
*xfm = NULL;
}
static struct transform *dce80_transform_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce80_transform_reg_offsets *offsets)
+ uint32_t inst)
{
- struct dce80_transform *transform =
- dm_alloc(sizeof(struct dce80_transform));
+ struct dce110_transform *transform =
+ dm_alloc(sizeof(struct dce110_transform));
if (!transform)
return NULL;
- if (dce80_transform_construct(transform, ctx, inst, offsets))
+ if (dce110_transform_construct(transform, ctx, inst,
+ &xfm_regs[inst], &xfm_shift, &xfm_mask)) {
+ transform->prescaler_on = false;
+ transform->base.lb_memory_size = 0x6B0; /*1712*/
return &transform->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(transform);
@@ -1028,8 +1010,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.transforms[i] = dce80_transform_create(
- ctx, i, &dce80_xfm_offsets[i]);
+ pool->base.transforms[i] = dce80_transform_create(ctx, i);
if (pool->base.transforms[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create transform!\n");
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
deleted file mode 100644
index e2187608fd62..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/* include DCE8 register header files */
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-#include "dc_types.h"
-#include "core_types.h"
-
-#include "include/grph_object_id.h"
-#include "include/fixed31_32.h"
-#include "include/logger_interface.h"
-
-#include "dce80_transform.h"
-
-#include "dce80_transform_bit_depth.h"
-
-bool dce80_transform_get_optimal_number_of_taps(
- struct transform *xfm,
- struct scaler_data *scl_data,
- const struct scaling_taps *in_taps)
-{
-
- return transform_get_optimal_number_of_taps_helper(
- xfm,
- scl_data,
- scl_data->viewport.width,
- in_taps);
-
- return true;
-}
-
-static void dce80_transform_reset(struct transform *xfm)
-{
-}
-
-
-static const struct transform_funcs dce80_transform_funcs = {
- .transform_reset = dce80_transform_reset,
- .transform_set_scaler =
- dce80_transform_set_scaler,
- .transform_set_gamut_remap =
- dce80_transform_set_gamut_remap,
- .transform_set_pixel_storage_depth =
- dce80_transform_set_pixel_storage_depth,
- .transform_get_optimal_number_of_taps =
- dce80_transform_get_optimal_number_of_taps
-};
-
-/*****************************************/
-/* Constructor, Destructor */
-/*****************************************/
-
-bool dce80_transform_construct(
- struct dce80_transform *xfm80,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce80_transform_reg_offsets *reg_offsets)
-{
- xfm80->base.ctx = ctx;
-
- xfm80->base.inst = inst;
- xfm80->base.funcs = &dce80_transform_funcs;
-
- xfm80->offsets = *reg_offsets;
-
- xfm80->lb_pixel_depth_supported =
- LB_PIXEL_DEPTH_18BPP |
- LB_PIXEL_DEPTH_24BPP |
- LB_PIXEL_DEPTH_30BPP;
-
- xfm80->base.lb_bits_per_entry = LB_BITS_PER_ENTRY;
- xfm80->base.lb_total_entries_num = LB_TOTAL_NUMBER_OF_ENTRIES;
-
- xfm80->base.lb_memory_size = 0x6B0; /*1712*/
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
deleted file mode 100644
index 92299e36e3dd..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_TRANSFORM_DCE80_H__
-#define __DAL_TRANSFORM_DCE80_H__
-
-#include "transform.h"
-
-#define TO_DCE80_TRANSFORM(transform)\
- container_of(transform, struct dce80_transform, base)
-
-#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
-#define LB_BITS_PER_ENTRY 144
-
-struct dce80_transform_reg_offsets {
- uint32_t scl_offset;
- uint32_t crtc_offset;
- uint32_t dcp_offset;
- uint32_t lb_offset;
-};
-
-struct dce80_transform {
- struct transform base;
- struct dce80_transform_reg_offsets offsets;
-
- uint32_t lb_pixel_depth_supported;
-};
-
-bool dce80_transform_construct(struct dce80_transform *xfm80,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce80_transform_reg_offsets *offsets);
-
-/* SCALER RELATED */
-void dce80_transform_set_scaler(
- struct transform *xfm,
- const struct scaler_data *data);
-
-void dce80_transform_set_scaler_filter(
- struct transform *xfm,
- struct scaler_filter *filter);
-
-/* GAMUT RELATED */
-void dce80_transform_set_gamut_remap(
- struct transform *xfm,
- const struct xfm_grph_csc_adjustment *adjust);
-
-/* BIT DEPTH RELATED */
-void dce80_transform_set_pixel_storage_depth(
- struct transform *xfm,
- enum lb_pixel_depth depth,
- const struct bit_depth_reduction_params *bit_depth_params);
-
-#endif
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
deleted file mode 100644
index e74f7cfb0fe9..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
+++ /dev/null
@@ -1,671 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/* include DCE8 register header files */
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-#include "dce80_transform.h"
-
-#include "include/logger_interface.h"
-#include "include/fixed32_32.h"
-
-#define DCP_REG(reg)\
- (reg + xfm80->offsets.dcp_offset)
-
-#define LB_REG(reg)\
- (reg + xfm80->offsets.lb_offset)
-
-enum dcp_out_trunc_round_mode {
- DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
- DCP_OUT_TRUNC_ROUND_MODE_ROUND
-};
-
-enum dcp_out_trunc_round_depth {
- DCP_OUT_TRUNC_ROUND_DEPTH_14BIT,
- DCP_OUT_TRUNC_ROUND_DEPTH_13BIT,
- DCP_OUT_TRUNC_ROUND_DEPTH_12BIT,
- DCP_OUT_TRUNC_ROUND_DEPTH_11BIT,
- DCP_OUT_TRUNC_ROUND_DEPTH_10BIT,
- DCP_OUT_TRUNC_ROUND_DEPTH_9BIT,
- DCP_OUT_TRUNC_ROUND_DEPTH_8BIT
-};
-
-/* defines the various methods of bit reduction available for use */
-enum dcp_bit_depth_reduction_mode {
- DCP_BIT_DEPTH_REDUCTION_MODE_DITHER,
- DCP_BIT_DEPTH_REDUCTION_MODE_ROUND,
- DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE,
- DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED,
- DCP_BIT_DEPTH_REDUCTION_MODE_INVALID
-};
-
-enum dcp_spatial_dither_mode {
- DCP_SPATIAL_DITHER_MODE_AAAA,
- DCP_SPATIAL_DITHER_MODE_A_AA_A,
- DCP_SPATIAL_DITHER_MODE_AABBAABB,
- DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC,
- DCP_SPATIAL_DITHER_MODE_INVALID
-};
-
-enum dcp_spatial_dither_depth {
- DCP_SPATIAL_DITHER_DEPTH_30BPP,
- DCP_SPATIAL_DITHER_DEPTH_24BPP
-};
-
-static bool set_clamp(
- struct dce80_transform *xfm80,
- enum dc_color_depth depth);
-
-static bool set_round(
- struct dce80_transform *xfm80,
- enum dcp_out_trunc_round_mode mode,
- enum dcp_out_trunc_round_depth depth);
-
-static bool set_dither(
- struct dce80_transform *xfm80,
- bool dither_enable,
- enum dcp_spatial_dither_mode dither_mode,
- enum dcp_spatial_dither_depth dither_depth,
- bool frame_random_enable,
- bool rgb_random_enable,
- bool highpass_random_enable);
-
-/**
- *******************************************************************************
- * dce80_transform_bit_depth_reduction_program
- *
- * @brief
- * Programs the DCP bit depth reduction registers (Clamp, Round/Truncate,
- * Dither) for dce80
- *
- * @param depth : bit depth to set the clamp to (should match denorm)
- *
- * @return
- * true if succeeds.
- *******************************************************************************
- */
-static bool program_bit_depth_reduction(
- struct dce80_transform *xfm80,
- enum dc_color_depth depth)
-{
- enum dcp_bit_depth_reduction_mode depth_reduction_mode;
- enum dcp_spatial_dither_mode spatial_dither_mode;
- bool frame_random_enable;
- bool rgb_random_enable;
- bool highpass_random_enable;
-
- if (depth > COLOR_DEPTH_121212) {
- ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
- return false;
- }
-
- depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DITHER;
-
- spatial_dither_mode = DCP_SPATIAL_DITHER_MODE_A_AA_A;
-
- frame_random_enable = true;
- rgb_random_enable = true;
- highpass_random_enable = true;
-
- if (!set_clamp(xfm80, depth)) {
- /* Failure in set_clamp() */
- ASSERT_CRITICAL(false);
- return false;
- }
- switch (depth_reduction_mode) {
- case DCP_BIT_DEPTH_REDUCTION_MODE_DITHER:
- /* Spatial Dither: Set round/truncate to bypass (12bit),
- * enable Dither (30bpp) */
- set_round(xfm80,
- DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
- DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-
- set_dither(xfm80, true, spatial_dither_mode,
- DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
- rgb_random_enable, highpass_random_enable);
- break;
- case DCP_BIT_DEPTH_REDUCTION_MODE_ROUND:
- /* Round: Enable round (10bit), disable Dither */
- set_round(xfm80,
- DCP_OUT_TRUNC_ROUND_MODE_ROUND,
- DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-
- set_dither(xfm80, false, spatial_dither_mode,
- DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
- rgb_random_enable, highpass_random_enable);
- break;
- case DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE: /* Truncate */
- /* Truncate: Enable truncate (10bit), disable Dither */
- set_round(xfm80,
- DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
- DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-
- set_dither(xfm80, false, spatial_dither_mode,
- DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
- rgb_random_enable, highpass_random_enable);
- break;
-
- case DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED: /* Disabled */
- /* Truncate: Set round/truncate to bypass (12bit),
- * disable Dither */
- set_round(xfm80,
- DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
- DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-
- set_dither(xfm80, false, spatial_dither_mode,
- DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
- rgb_random_enable, highpass_random_enable);
- break;
- default:
- /* Invalid DCP Depth reduction mode */
- ASSERT_CRITICAL(false);
- break;
- }
-
- return true;
-}
-
-/**
- *******************************************************************************
- * set_clamp
- *
- * @param depth : bit depth to set the clamp to (should match denorm)
- *
- * @brief
- * Programs clamp according to panel bit depth.
- *
- * @return
- * true if succeeds
- *
- *******************************************************************************
- */
-static bool set_clamp(
- struct dce80_transform *xfm80,
- enum dc_color_depth depth)
-{
- uint32_t clamp_max = 0;
-
- /* At the clamp block the data will be MSB aligned, so we set the max
- * clamp accordingly.
- * For example, the max value for 6 bits MSB aligned (14 bit bus) would
- * be "11 1111 0000 0000" in binary, so 0x3F00.
- */
- switch (depth) {
- case COLOR_DEPTH_666:
- /* 6bit MSB aligned on 14 bit bus '11 1111 0000 0000' */
- clamp_max = 0x3F00;
- break;
- case COLOR_DEPTH_888:
- /* 8bit MSB aligned on 14 bit bus '11 1111 800 0000' */
- clamp_max = 0x3FC0;
- break;
- case COLOR_DEPTH_101010:
- /* 10bit MSB aligned on 14 bit bus '11 1111 1111 800' */
- clamp_max = 0x3FFC;
- break;
- case COLOR_DEPTH_121212:
- /* 12bit MSB aligned on 14 bit bus '11 1111 1111 1111' */
- clamp_max = 0x3FFF;
- break;
- default:
- ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
- return false;
- }
-
- {
- uint32_t value = 0;
- /* always set min to 0 */
- set_reg_field_value(
- value,
- 0,
- OUT_CLAMP_CONTROL_B_CB,
- OUT_CLAMP_MIN_B_CB);
-
- set_reg_field_value(
- value,
- clamp_max,
- OUT_CLAMP_CONTROL_B_CB,
- OUT_CLAMP_MAX_B_CB);
-
- dm_write_reg(xfm80->base.ctx,
- DCP_REG(mmOUT_CLAMP_CONTROL_B_CB),
- value);
- }
-
- {
- uint32_t value = 0;
- /* always set min to 0 */
- set_reg_field_value(
- value,
- 0,
- OUT_CLAMP_CONTROL_G_Y,
- OUT_CLAMP_MIN_G_Y);
-
- set_reg_field_value(
- value,
- clamp_max,
- OUT_CLAMP_CONTROL_G_Y,
- OUT_CLAMP_MAX_G_Y);
-
- dm_write_reg(xfm80->base.ctx,
- DCP_REG(mmOUT_CLAMP_CONTROL_G_Y),
- value);
- }
-
- {
- uint32_t value = 0;
- /* always set min to 0 */
- set_reg_field_value(
- value,
- 0,
- OUT_CLAMP_CONTROL_R_CR,
- OUT_CLAMP_MIN_R_CR);
-
- set_reg_field_value(
- value,
- clamp_max,
- OUT_CLAMP_CONTROL_R_CR,
- OUT_CLAMP_MAX_R_CR);
-
- dm_write_reg(xfm80->base.ctx,
- DCP_REG(mmOUT_CLAMP_CONTROL_R_CR),
- value);
- }
-
- return true;
-}
-
-/**
- *******************************************************************************
- * set_round
- *
- * @brief
- * Programs Round/Truncate
- *
- * @param [in] mode :round or truncate
- * @param [in] depth :bit depth to round/truncate to
- OUT_ROUND_TRUNC_MODE 3:0 0xA Output data round or truncate mode
- POSSIBLE VALUES:
- 00 - truncate to u0.12
- 01 - truncate to u0.11
- 02 - truncate to u0.10
- 03 - truncate to u0.9
- 04 - truncate to u0.8
- 05 - reserved
- 06 - truncate to u0.14
- 07 - truncate to u0.13 set_reg_field_value(
- value,
- clamp_max,
- OUT_CLAMP_CONTROL_R_CR,
- OUT_CLAMP_MAX_R_CR);
- 08 - round to u0.12
- 09 - round to u0.11
- 10 - round to u0.10
- 11 - round to u0.9
- 12 - round to u0.8
- 13 - reserved
- 14 - round to u0.14
- 15 - round to u0.13
-
- * @return
- * true if succeeds.
- *******************************************************************************
- */
-static bool set_round(
- struct dce80_transform *xfm80,
- enum dcp_out_trunc_round_mode mode,
- enum dcp_out_trunc_round_depth depth)
-{
- uint32_t depth_bits = 0;
- uint32_t mode_bit = 0;
- /* zero out all bits */
- uint32_t value = 0;
-
- /* set up bit depth */
- switch (depth) {
- case DCP_OUT_TRUNC_ROUND_DEPTH_14BIT:
- depth_bits = 6;
- break;
- case DCP_OUT_TRUNC_ROUND_DEPTH_13BIT:
- depth_bits = 7;
- break;
- case DCP_OUT_TRUNC_ROUND_DEPTH_12BIT:
- depth_bits = 0;
- break;
- case DCP_OUT_TRUNC_ROUND_DEPTH_11BIT:
- depth_bits = 1;
- break;
- case DCP_OUT_TRUNC_ROUND_DEPTH_10BIT:
- depth_bits = 2;
- break;
- case DCP_OUT_TRUNC_ROUND_DEPTH_9BIT:
- depth_bits = 3;
- break;
- case DCP_OUT_TRUNC_ROUND_DEPTH_8BIT:
- depth_bits = 4;
- break;
- default:
- /* Invalid dcp_out_trunc_round_depth */
- ASSERT_CRITICAL(false);
- return false;
- }
-
- set_reg_field_value(
- value,
- depth_bits,
- OUT_ROUND_CONTROL,
- OUT_ROUND_TRUNC_MODE);
-
- /* set up round or truncate */
- switch (mode) {
- case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE:
- mode_bit = 0;
- break;
- case DCP_OUT_TRUNC_ROUND_MODE_ROUND:
- mode_bit = 1;
- break;
- default:
- /* Invalid dcp_out_trunc_round_mode */
- ASSERT_CRITICAL(false);
- return false;
- }
-
- depth_bits |= mode_bit << 3;
-
- set_reg_field_value(
- value,
- depth_bits,
- OUT_ROUND_CONTROL,
- OUT_ROUND_TRUNC_MODE);
-
- /* write the register */
- dm_write_reg(xfm80->base.ctx,
- DCP_REG(mmOUT_ROUND_CONTROL),
- value);
-
- return true;
-}
-
-/**
- *******************************************************************************
- * set_dither
- *
- * @brief
- * Programs Dither
- *
- * @param [in] dither_enable : enable dither
- * @param [in] dither_mode : dither mode to set
- * @param [in] dither_depth : bit depth to dither to
- * @param [in] frame_random_enable : enable frame random
- * @param [in] rgb_random_enable : enable rgb random
- * @param [in] highpass_random_enable : enable highpass random
- *
- * @return
- * true if succeeds.
- *******************************************************************************
- */
-
-static bool set_dither(
- struct dce80_transform *xfm80,
- bool dither_enable,
- enum dcp_spatial_dither_mode dither_mode,
- enum dcp_spatial_dither_depth dither_depth,
- bool frame_random_enable,
- bool rgb_random_enable,
- bool highpass_random_enable)
-{
- uint32_t dither_depth_bits = 0;
- uint32_t dither_mode_bits = 0;
- /* zero out all bits */
- uint32_t value = 0;
-
- /* set up the fields */
- if (dither_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_SPATIAL_DITHER_EN);
-
- switch (dither_mode) {
- case DCP_SPATIAL_DITHER_MODE_AAAA:
- dither_mode_bits = 0;
- break;
- case DCP_SPATIAL_DITHER_MODE_A_AA_A:
- dither_mode_bits = 1;
- break;
- case DCP_SPATIAL_DITHER_MODE_AABBAABB:
- dither_mode_bits = 2;
- break;
- case DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC:
- dither_mode_bits = 3;
- break;
- default:
- /* Invalid dcp_spatial_dither_mode */
- ASSERT_CRITICAL(false);
- return false;
-
- }
- set_reg_field_value(
- value,
- dither_mode_bits,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_SPATIAL_DITHER_MODE);
-
- switch (dither_depth) {
- case DCP_SPATIAL_DITHER_DEPTH_30BPP:
- dither_depth_bits = 0;
- break;
- case DCP_SPATIAL_DITHER_DEPTH_24BPP:
- dither_depth_bits = 1;
- break;
- default:
- /* Invalid dcp_spatial_dither_depth */
- ASSERT_CRITICAL(false);
- return false;
- }
-
- set_reg_field_value(
- value,
- dither_depth_bits,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_SPATIAL_DITHER_DEPTH);
-
- if (frame_random_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_FRAME_RANDOM_ENABLE);
-
- if (rgb_random_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_RGB_RANDOM_ENABLE);
-
- if (highpass_random_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_HIGHPASS_RANDOM_ENABLE);
-
- /* write the register */
- dm_write_reg(xfm80->base.ctx,
- DCP_REG(mmDCP_SPATIAL_DITHER_CNTL),
- value);
-
- return true;
-}
-
-void dce80_transform_enable_alpha(
- struct dce80_transform *xfm80,
- bool enable)
-{
- struct dc_context *ctx = xfm80->base.ctx;
- uint32_t value;
- uint32_t addr = LB_REG(mmLB_DATA_FORMAT);
-
- value = dm_read_reg(ctx, addr);
-
- if (enable == 1)
- set_reg_field_value(
- value,
- 1,
- LB_DATA_FORMAT,
- ALPHA_EN);
- else
- set_reg_field_value(
- value,
- 0,
- LB_DATA_FORMAT,
- ALPHA_EN);
-
- dm_write_reg(ctx, addr, value);
-}
-
-bool dce80_transform_is_prefetch_enabled(
- struct dce80_transform *xfm80)
-{
- uint32_t value = dm_read_reg(
- xfm80->base.ctx, LB_REG(mmLB_DATA_FORMAT));
-
- if (get_reg_field_value(value, LB_DATA_FORMAT, PREFETCH) == 1)
- return true;
-
- return false;
-}
-
-static void set_denormalization(
- struct dce80_transform *xfm80,
- enum dc_color_depth depth)
-{
- uint32_t value = dm_read_reg(xfm80->base.ctx,
- DCP_REG(mmDENORM_CONTROL));
-
- switch (depth) {
- case COLOR_DEPTH_666:
- /* 63/64 for 6 bit output color depth */
- set_reg_field_value(
- value,
- 1,
- DENORM_CONTROL,
- DENORM_MODE);
- break;
- case COLOR_DEPTH_888:
- /* Unity for 8 bit output color depth
- * because prescale is disabled by default */
- set_reg_field_value(
- value,
- 0,
- DENORM_CONTROL,
- DENORM_MODE);
- break;
- case COLOR_DEPTH_101010:
- /* 1023/1024 for 10 bit output color depth */
- set_reg_field_value(
- value,
- 3,
- DENORM_CONTROL,
- DENORM_MODE);
- break;
- case COLOR_DEPTH_121212:
- /* 4095/4096 for 12 bit output color depth */
- set_reg_field_value(
- value,
- 5,
- DENORM_CONTROL,
- DENORM_MODE);
- break;
- case COLOR_DEPTH_141414:
- case COLOR_DEPTH_161616:
- default:
- /* not valid used case! */
- break;
- }
-
- dm_write_reg(xfm80->base.ctx,
- DCP_REG(mmDENORM_CONTROL),
- value);
-
-}
-
-void dce80_transform_set_pixel_storage_depth(
- struct transform *xfm,
- enum lb_pixel_depth depth,
- const struct bit_depth_reduction_params *bit_depth_params)
-{
- struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- uint32_t value;
- enum dc_color_depth color_depth;
-
- value = dm_read_reg(
- xfm->ctx,
- LB_REG(mmLB_DATA_FORMAT));
- switch (depth) {
- case LB_PIXEL_DEPTH_18BPP:
- color_depth = COLOR_DEPTH_666;
- set_reg_field_value(value, 2, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
- break;
- case LB_PIXEL_DEPTH_24BPP:
- color_depth = COLOR_DEPTH_888;
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
- break;
- case LB_PIXEL_DEPTH_30BPP:
- color_depth = COLOR_DEPTH_101010;
- set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
- break;
- case LB_PIXEL_DEPTH_36BPP:
- color_depth = COLOR_DEPTH_121212;
- set_reg_field_value(value, 3, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
- break;
- default:
- break;
- }
-
- set_denormalization(xfm80, color_depth);
- program_bit_depth_reduction(xfm80, color_depth);
-
- set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
- dm_write_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
- if (!(xfm80->lb_pixel_depth_supported & depth)) {
- /*we should use unsupported capabilities
- * unless it is required by w/a*/
- dm_logger_write(xfm->ctx->logger, LOG_WARNING,
- "%s: Capability not supported",
- __func__);
- }
-}
-
-
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
deleted file mode 100644
index beecefba16a5..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_TRANSFORM_BIT_DEPTH_DCE80_H__
-#define __DC_TRANSFORM_BIT_DEPTH_DCE80_H__
-
-#include "dce80_transform.h"
-
-void dce80_transform_enable_alpha(
- struct dce80_transform *xfm80,
- bool enable);
-
-bool dce80_transform_is_prefetch_enabled(
- struct dce80_transform *xfm80);
-
-#endif
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
deleted file mode 100644
index 45f15d449247..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "dce80_transform.h"
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-#include "include/fixed31_32.h"
-#include "basics/conversion.h"
-#include "include/grph_object_id.h"
-
-enum {
- GAMUT_MATRIX_SIZE = 12
-};
-
-#define DCP_REG(reg)\
- (reg + xfm80->offsets.dcp_offset)
-
-#define DISP_BRIGHTNESS_DEFAULT_HW 0
-#define DISP_BRIGHTNESS_MIN_HW -25
-#define DISP_BRIGHTNESS_MAX_HW 25
-#define DISP_BRIGHTNESS_STEP_HW 1
-#define DISP_BRIGHTNESS_HW_DIVIDER 100
-
-#define DISP_HUE_DEFAULT_HW 0
-#define DISP_HUE_MIN_HW -30
-#define DISP_HUE_MAX_HW 30
-#define DISP_HUE_STEP_HW 1
-#define DISP_HUE_HW_DIVIDER 1
-
-#define DISP_CONTRAST_DEFAULT_HW 100
-#define DISP_CONTRAST_MIN_HW 50
-#define DISP_CONTRAST_MAX_HW 150
-#define DISP_CONTRAST_STEP_HW 1
-#define DISP_CONTRAST_HW_DIVIDER 100
-
-#define DISP_SATURATION_DEFAULT_HW 100
-#define DISP_SATURATION_MIN_HW 0
-#define DISP_SATURATION_MAX_HW 200
-#define DISP_SATURATION_STEP_HW 1
-#define DISP_SATURATION_HW_DIVIDER 100
-
-#define DISP_KELVIN_DEGRES_DEFAULT 6500
-#define DISP_KELVIN_DEGRES_MIN 4000
-#define DISP_KELVIN_DEGRES_MAX 10000
-#define DISP_KELVIN_DEGRES_STEP 100
-#define DISP_KELVIN_HW_DIVIDER 10000
-
-static void program_gamut_remap(
- struct dce80_transform *xfm80,
- const uint16_t *reg_val)
-{
- struct dc_context *ctx = xfm80->base.ctx;
- uint32_t value = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
-
- /* the register controls ovl also */
- value = dm_read_reg(ctx, addr);
-
- if (reg_val) {
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C11_C12);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[0],
- GAMUT_REMAP_C11_C12,
- GAMUT_REMAP_C11);
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[1],
- GAMUT_REMAP_C11_C12,
- GAMUT_REMAP_C12);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C13_C14);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[2],
- GAMUT_REMAP_C13_C14,
- GAMUT_REMAP_C13);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[3],
- GAMUT_REMAP_C13_C14,
- GAMUT_REMAP_C14);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C21_C22);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[4],
- GAMUT_REMAP_C21_C22,
- GAMUT_REMAP_C21);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[5],
- GAMUT_REMAP_C21_C22,
- GAMUT_REMAP_C22);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C23_C24);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[6],
- GAMUT_REMAP_C23_C24,
- GAMUT_REMAP_C23);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[7],
- GAMUT_REMAP_C23_C24,
- GAMUT_REMAP_C24);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C31_C32);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[8],
- GAMUT_REMAP_C31_C32,
- GAMUT_REMAP_C31);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[9],
- GAMUT_REMAP_C31_C32,
- GAMUT_REMAP_C32);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C33_C34);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[10],
- GAMUT_REMAP_C33_C34,
- GAMUT_REMAP_C33);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[11],
- GAMUT_REMAP_C33_C34,
- GAMUT_REMAP_C34);
-
- dm_write_reg(ctx, addr, reg_data);
- }
-
- set_reg_field_value(
- value,
- 1,
- GAMUT_REMAP_CONTROL,
- GRPH_GAMUT_REMAP_MODE);
-
- } else
- set_reg_field_value(
- value,
- 0,
- GAMUT_REMAP_CONTROL,
- GRPH_GAMUT_REMAP_MODE);
-
- addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
- dm_write_reg(ctx, addr, value);
-
-}
-
-/**
- *****************************************************************************
- * Function: dal_transform_wide_gamut_set_gamut_remap
- *
- * @param [in] const struct xfm_grph_csc_adjustment *adjust
- *
- * @return
- * void
- *
- * @note calculate and apply color temperature adjustment to in Rgb color space
- *
- * @see
- *
- *****************************************************************************
- */
-void dce80_transform_set_gamut_remap(
- struct transform *xfm,
- const struct xfm_grph_csc_adjustment *adjust)
-{
- struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-
- if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
- program_gamut_remap(xfm80, NULL);
- else {
- struct fixed31_32 arr_matrix[GAMUT_MATRIX_SIZE];
- uint16_t arr_reg_val[GAMUT_MATRIX_SIZE];
-
- arr_matrix[0] = adjust->temperature_matrix[0];
- arr_matrix[1] = adjust->temperature_matrix[1];
- arr_matrix[2] = adjust->temperature_matrix[2];
- arr_matrix[3] = dal_fixed31_32_zero;
-
- arr_matrix[4] = adjust->temperature_matrix[3];
- arr_matrix[5] = adjust->temperature_matrix[4];
- arr_matrix[6] = adjust->temperature_matrix[5];
- arr_matrix[7] = dal_fixed31_32_zero;
-
- arr_matrix[8] = adjust->temperature_matrix[6];
- arr_matrix[9] = adjust->temperature_matrix[7];
- arr_matrix[10] = adjust->temperature_matrix[8];
- arr_matrix[11] = dal_fixed31_32_zero;
-
- convert_float_matrix(
- arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE);
-
- program_gamut_remap(xfm80, arr_reg_val);
- }
-}
-
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
deleted file mode 100644
index caf4def8510f..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
+++ /dev/null
@@ -1,737 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/* include DCE8 register header files */
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-#include "dce80_transform.h"
-
-#define UP_SCALER_RATIO_MAX 16000
-#define DOWN_SCALER_RATIO_MAX 250
-#define SCALER_RATIO_DIVIDER 1000
-
-#define SCL_REG(reg)\
- (reg + xfm80->offsets.scl_offset)
-
-#define DCFE_REG(reg)\
- (reg + xfm80->offsets.crtc_offset)
-
-#define LB_REG(reg)\
- (reg + xfm80->offsets.lb_offset)
-
-static void disable_enhanced_sharpness(struct dce80_transform *xfm80)
-{
- uint32_t value;
-
- value = dm_read_reg(xfm80->base.ctx,
- SCL_REG(mmSCL_F_SHARP_CONTROL));
-
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_HF_SHARP_EN);
-
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_VF_SHARP_EN);
-
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_HF_SHARP_SCALE_FACTOR);
-
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_VF_SHARP_SCALE_FACTOR);
-
- dm_write_reg(xfm80->base.ctx,
- SCL_REG(mmSCL_F_SHARP_CONTROL), value);
-}
-
-static void dce80_transform_set_scaler_bypass(
- struct transform *xfm,
- const struct scaler_data *scl_data)
-{
- struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- uint32_t sclv_mode;
-
- disable_enhanced_sharpness(xfm80);
-
- sclv_mode = dm_read_reg(xfm->ctx, SCL_REG(mmSCL_MODE));
- set_reg_field_value(sclv_mode, 0, SCL_MODE, SCL_MODE);
- dm_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), sclv_mode);
-}
-
-/**
-* Function:
-* void setup_scaling_configuration
-*
-* Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
-* Input: data
-*
-* Output:
- void
-*/
-static bool setup_scaling_configuration(
- struct dce80_transform *xfm80,
- const struct scaler_data *data)
-{
- struct dc_context *ctx = xfm80->base.ctx;
- uint32_t addr;
- uint32_t value;
-
- if (data->taps.h_taps + data->taps.v_taps <= 2) {
- dce80_transform_set_scaler_bypass(&xfm80->base, NULL);
- return false;
- }
- {
- addr = SCL_REG(mmSCL_TAP_CONTROL);
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(value, data->taps.h_taps - 1,
- SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-
- set_reg_field_value(value, data->taps.v_taps - 1,
- SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-
- dm_write_reg(ctx, addr, value);
- }
- {
- addr = SCL_REG(mmSCL_MODE);
- value = dm_read_reg(ctx, addr);
-
- if (data->format <= PIXEL_FORMAT_GRPH_END)
- set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
- else
- set_reg_field_value(value, 2, SCL_MODE, SCL_MODE);
-
- dm_write_reg(ctx, addr, value);
- }
- {
- addr = SCL_REG(mmSCL_CONTROL);
- value = dm_read_reg(ctx, addr);
- /* 1 - Replaced out of bound pixels with edge */
- set_reg_field_value(value, 1, SCL_CONTROL, SCL_BOUNDARY_MODE);
-
- /* 1 - Replaced out of bound pixels with the edge pixel. */
- dm_write_reg(ctx, addr, value);
- }
-
- return true;
-}
-
-/**
-* Function:
-* void program_overscan
-*
-* Purpose: Programs overscan border
-* Input: overscan
-*
-* Output:
- void
-*/
-static void program_overscan(
- struct dce80_transform *xfm80,
- const struct scaler_data *data)
-{
- uint32_t overscan_left_right = 0;
- uint32_t overscan_top_bottom = 0;
-
- int overscan_right = data->h_active - data->recout.x - data->recout.width;
- int overscan_bottom = data->v_active - data->recout.y - data->recout.height;
-
- if (overscan_right < 0) {
- BREAK_TO_DEBUGGER();
- overscan_right = 0;
- }
- if (overscan_bottom < 0) {
- BREAK_TO_DEBUGGER();
- overscan_bottom = 0;
- }
-
- set_reg_field_value(overscan_left_right, data->recout.x,
- EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
-
- set_reg_field_value(overscan_left_right, overscan_right,
- EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
-
- set_reg_field_value(overscan_top_bottom, data->recout.y,
- EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
-
- set_reg_field_value(overscan_top_bottom, overscan_bottom,
- EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
-
- dm_write_reg(xfm80->base.ctx,
- SCL_REG(mmEXT_OVERSCAN_LEFT_RIGHT),
- overscan_left_right);
-
- dm_write_reg(xfm80->base.ctx,
- SCL_REG(mmEXT_OVERSCAN_TOP_BOTTOM),
- overscan_top_bottom);
-}
-
-static void program_two_taps_filter(
- struct dce80_transform *xfm80,
- bool enable,
- bool vertical)
-{
- uint32_t addr;
- uint32_t value;
- /* 1: Hard coded 2 tap filter
- * 0: Programmable 2 tap filter from coefficient RAM
- */
- if (vertical) {
- addr = SCL_REG(mmSCL_VERT_FILTER_CONTROL);
- value = dm_read_reg(xfm80->base.ctx, addr);
- set_reg_field_value(
- value,
- enable ? 1 : 0,
- SCL_VERT_FILTER_CONTROL,
- SCL_V_2TAP_HARDCODE_COEF_EN);
-
- } else {
- addr = SCL_REG(mmSCL_HORZ_FILTER_CONTROL);
- value = dm_read_reg(xfm80->base.ctx, addr);
- set_reg_field_value(
- value,
- enable ? 1 : 0,
- SCL_HORZ_FILTER_CONTROL,
- SCL_H_2TAP_HARDCODE_COEF_EN);
- }
-
- dm_write_reg(xfm80->base.ctx, addr, value);
-}
-
-static void set_coeff_update_complete(struct dce80_transform *xfm80)
-{
- uint32_t value;
- uint32_t addr = SCL_REG(mmSCL_UPDATE);
-
- value = dm_read_reg(xfm80->base.ctx, addr);
- set_reg_field_value(value, 1,
- SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
- dm_write_reg(xfm80->base.ctx, addr, value);
-}
-
-static void program_filter(
- struct dce80_transform *xfm80,
- enum ram_filter_type filter_type,
- struct scaler_filter_params *scl_filter_params,
- uint32_t *coeffs,
- uint32_t coeffs_num)
-{
- uint32_t phase = 0;
- uint32_t array_idx = 0;
- uint32_t pair = 0;
-
- uint32_t taps_pairs = (scl_filter_params->taps + 1) / 2;
- uint32_t phases_to_program = scl_filter_params->phases / 2 + 1;
-
- uint32_t i;
- uint32_t addr;
- uint32_t select_addr;
- uint32_t select;
- uint32_t data;
- /* We need to disable power gating on coeff memory to do programming */
-
- uint32_t pwr_ctrl_orig;
- uint32_t pwr_ctrl_off;
-
- addr = DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL);
- pwr_ctrl_orig = dm_read_reg(xfm80->base.ctx, addr);
- pwr_ctrl_off = pwr_ctrl_orig;
- set_reg_field_value(
- pwr_ctrl_off,
- 1,
- DCFE_MEM_LIGHT_SLEEP_CNTL,
- SCL_LIGHT_SLEEP_DIS);
- dm_write_reg(xfm80->base.ctx, addr, pwr_ctrl_off);
-
- /* Wait to disable gating: */
- for (i = 0;
- i < 10 &&
- get_reg_field_value(
- dm_read_reg(xfm80->base.ctx, addr),
- DCFE_MEM_LIGHT_SLEEP_CNTL,
- SCL_MEM_PWR_STATE);
- i++)
- udelay(1);
-
- ASSERT(i < 10);
-
- select_addr = SCL_REG(mmSCL_COEF_RAM_SELECT);
- select = dm_read_reg(xfm80->base.ctx, select_addr);
-
- set_reg_field_value(
- select,
- filter_type,
- SCL_COEF_RAM_SELECT,
- SCL_C_RAM_FILTER_TYPE);
- set_reg_field_value(
- select,
- 0,
- SCL_COEF_RAM_SELECT,
- SCL_C_RAM_TAP_PAIR_IDX);
- set_reg_field_value(
- select,
- 0,
- SCL_COEF_RAM_SELECT,
- SCL_C_RAM_PHASE);
-
- data = 0;
-
- for (phase = 0; phase < phases_to_program; phase++) {
- /* we always program N/2 + 1 phases, total phases N, but N/2-1
- * are just mirror phase 0 is unique and phase N/2 is unique
- * if N is even
- */
-
- set_reg_field_value(
- select,
- phase,
- SCL_COEF_RAM_SELECT,
- SCL_C_RAM_PHASE);
-
- for (pair = 0; pair < taps_pairs; pair++) {
- set_reg_field_value(
- select,
- pair,
- SCL_COEF_RAM_SELECT,
- SCL_C_RAM_TAP_PAIR_IDX);
- dm_write_reg(xfm80->base.ctx, select_addr, select);
-
- /* even tap write enable */
- set_reg_field_value(
- data,
- 1,
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_EVEN_TAP_COEF_EN);
- /* even tap data */
- set_reg_field_value(
- data,
- coeffs[array_idx],
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_EVEN_TAP_COEF);
-
- /* if we have odd number of taps and the last pair is
- * here then we do not need to program
- */
- if (scl_filter_params->taps % 2 &&
- pair == taps_pairs - 1) {
- /* odd tap write disable */
- set_reg_field_value(
- data,
- 0,
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_ODD_TAP_COEF_EN);
- set_reg_field_value(
- data,
- 0,
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_ODD_TAP_COEF);
- array_idx += 1;
- } else {
- /* odd tap write enable */
- set_reg_field_value(
- data,
- 1,
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_ODD_TAP_COEF_EN);
- /* dbg_val: 0x1000 / sclFilterParams->taps; */
- set_reg_field_value(
- data,
- coeffs[array_idx + 1],
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_ODD_TAP_COEF);
-
- array_idx += 2;
- }
-
- dm_write_reg(
- xfm80->base.ctx,
- SCL_REG(mmSCL_COEF_RAM_TAP_DATA),
- data);
- }
- }
-
- ASSERT(coeffs_num == array_idx);
-
- /* reset the power gating register */
- dm_write_reg(
- xfm80->base.ctx,
- DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL),
- pwr_ctrl_orig);
-
- set_coeff_update_complete(xfm80);
-}
-
-/*
- *
- * Populates an array with filter coefficients in 1.1.12 fixed point form
-*/
-static bool get_filter_coefficients(
- struct dce80_transform *xfm80,
- uint32_t taps,
- uint32_t **data_tab,
- uint32_t *data_size)
-{
- uint32_t num = 0;
- uint32_t i;
- const struct fixed31_32 *filter =
- dal_scaler_filter_get(
- xfm80->base.filter,
- data_tab,
- &num);
- uint32_t *data_row;
-
- if (!filter) {
- BREAK_TO_DEBUGGER();
- return false;
- }
- data_row = *data_tab;
-
- for (i = 0; i < num; ++i) {
- /* req. format sign fixed 1.1.12, the values are always between
- * [-1; 1]
- *
- * Each phase is mirrored as follows :
- * 0 : Phase 0
- * 1 : Phase 1 or Phase 64 - 1 / 128 - 1
- * N : Phase N or Phase 64 - N / 128 - N
- *
- * Convert from Fixed31_32 to 1.1.12 by using floor on value
- * shifted by number of required fractional bits(12)
- */
- struct fixed31_32 value = filter[i];
-
- data_row[i] =
- dal_fixed31_32_floor(dal_fixed31_32_shl(value, 12)) &
- 0x3FFC;
- }
- *data_size = num;
-
- return true;
-}
-
-static bool program_multi_taps_filter(
- struct dce80_transform *xfm80,
- const struct scaler_data *data,
- bool horizontal)
-{
- struct scaler_filter_params filter_params;
- enum ram_filter_type filter_type;
- uint32_t src_size;
- uint32_t dst_size;
-
- uint32_t *filter_data = NULL;
- uint32_t filter_data_size = 0;
-
- /* 16 phases total for DCE8 */
- filter_params.phases = 16;
-
- if (horizontal) {
- filter_params.taps = data->taps.h_taps;
- filter_params.sharpness = 0; /* TODO */
- filter_params.flags.bits.HORIZONTAL = 1;
-
- src_size = data->viewport.width;
- dst_size =
- dal_fixed31_32_floor(
- dal_fixed31_32_div(
- dal_fixed31_32_from_int(
- data->viewport.width),
- data->ratios.horz));
-
- filter_type = FILTER_TYPE_RGB_Y_HORIZONTAL;
- } else {
- filter_params.taps = data->taps.v_taps;
- filter_params.sharpness = 0; /* TODO */
- filter_params.flags.bits.HORIZONTAL = 0;
-
- src_size = data->viewport.height;
- dst_size =
- dal_fixed31_32_floor(
- dal_fixed31_32_div(
- dal_fixed31_32_from_int(
- data->viewport.height),
- data->ratios.vert));
-
- filter_type = FILTER_TYPE_RGB_Y_VERTICAL;
- }
-
- /* 1. Generate the coefficients */
- if (!dal_scaler_filter_generate(
- xfm80->base.filter,
- &filter_params,
- src_size,
- dst_size))
- return false;
-
- /* 2. Convert coefficients to fixed point format 1.12 (note coeff.
- * could be negative(!) and range is [ from -1 to 1 ]) */
- if (!get_filter_coefficients(
- xfm80,
- filter_params.taps,
- &filter_data,
- &filter_data_size))
- return false;
-
- /* 3. Program the filter */
- program_filter(
- xfm80,
- filter_type,
- &filter_params,
- filter_data,
- filter_data_size);
-
- return true;
-}
-
-static void program_viewport(
- struct dce80_transform *xfm80,
- const struct rect *view_port)
-{
- struct dc_context *ctx = xfm80->base.ctx;
- uint32_t value = 0;
- uint32_t addr = 0;
-
- addr = SCL_REG(mmVIEWPORT_START);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- view_port->x,
- VIEWPORT_START,
- VIEWPORT_X_START);
- set_reg_field_value(
- value,
- view_port->y,
- VIEWPORT_START,
- VIEWPORT_Y_START);
- dm_write_reg(ctx, addr, value);
-
- addr = SCL_REG(mmVIEWPORT_SIZE);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- view_port->height,
- VIEWPORT_SIZE,
- VIEWPORT_HEIGHT);
- set_reg_field_value(
- value,
- view_port->width,
- VIEWPORT_SIZE,
- VIEWPORT_WIDTH);
- dm_write_reg(ctx, addr, value);
-
- /* TODO: add stereo support */
-}
-
-static void calculate_inits(
- struct dce80_transform *xfm80,
- const struct scaler_data *data,
- struct scl_ratios_inits *inits)
-{
- struct fixed31_32 h_init;
- struct fixed31_32 v_init;
-
- inits->h_int_scale_ratio =
- dal_fixed31_32_u2d19(data->ratios.horz) << 5;
- inits->v_int_scale_ratio =
- dal_fixed31_32_u2d19(data->ratios.vert) << 5;
-
- h_init =
- dal_fixed31_32_div_int(
- dal_fixed31_32_add(
- data->ratios.horz,
- dal_fixed31_32_from_int(data->taps.h_taps + 1)),
- 2);
- inits->h_init.integer = dal_fixed31_32_floor(h_init);
- inits->h_init.fraction = dal_fixed31_32_u0d19(h_init) << 5;
-
- v_init =
- dal_fixed31_32_div_int(
- dal_fixed31_32_add(
- data->ratios.vert,
- dal_fixed31_32_from_int(data->taps.v_taps + 1)),
- 2);
- inits->v_init.integer = dal_fixed31_32_floor(v_init);
- inits->v_init.fraction = dal_fixed31_32_u0d19(v_init) << 5;
-}
-
-static void program_scl_ratios_inits(
- struct dce80_transform *xfm80,
- struct scl_ratios_inits *inits)
-{
- uint32_t addr = SCL_REG(mmSCL_HORZ_FILTER_SCALE_RATIO);
- uint32_t value = 0;
-
- set_reg_field_value(
- value,
- inits->h_int_scale_ratio,
- SCL_HORZ_FILTER_SCALE_RATIO,
- SCL_H_SCALE_RATIO);
- dm_write_reg(xfm80->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_VERT_FILTER_SCALE_RATIO);
- value = 0;
- set_reg_field_value(
- value,
- inits->v_int_scale_ratio,
- SCL_VERT_FILTER_SCALE_RATIO,
- SCL_V_SCALE_RATIO);
- dm_write_reg(xfm80->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_HORZ_FILTER_INIT);
- value = 0;
- set_reg_field_value(
- value,
- inits->h_init.integer,
- SCL_HORZ_FILTER_INIT,
- SCL_H_INIT_INT);
- set_reg_field_value(
- value,
- inits->h_init.fraction,
- SCL_HORZ_FILTER_INIT,
- SCL_H_INIT_FRAC);
- dm_write_reg(xfm80->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_VERT_FILTER_INIT);
- value = 0;
- set_reg_field_value(
- value,
- inits->v_init.integer,
- SCL_VERT_FILTER_INIT,
- SCL_V_INIT_INT);
- set_reg_field_value(
- value,
- inits->v_init.fraction,
- SCL_VERT_FILTER_INIT,
- SCL_V_INIT_FRAC);
- dm_write_reg(xfm80->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_AUTOMATIC_MODE_CONTROL);
- value = 0;
- set_reg_field_value(
- value,
- 0,
- SCL_AUTOMATIC_MODE_CONTROL,
- SCL_V_CALC_AUTO_RATIO_EN);
- set_reg_field_value(
- value,
- 0,
- SCL_AUTOMATIC_MODE_CONTROL,
- SCL_H_CALC_AUTO_RATIO_EN);
- dm_write_reg(xfm80->base.ctx, addr, value);
-}
-
-/* LB_MEMORY_CONFIG
- * 00 - Use all three pieces of memory
- * 01 - Use only one piece of memory of total 720x144 bits
- * 10 - Use two pieces of memory of total 960x144 bits
- * 11 - reserved
- *
- * LB_MEMORY_SIZE
- * Total entries of LB memory.
- * This number should be larger than 960. The default value is 1712(0x6B0) */
-static bool dce80_transform_power_up_line_buffer(struct transform *xfm)
-{
- struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- uint32_t value;
-
- value = dm_read_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
-
- /*Use all three pieces of memory always*/
- set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
- /*hard coded number DCE8 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, xfm80->base.lb_memory_size, LB_MEMORY_CTRL,
- LB_MEMORY_SIZE);
-
- dm_write_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
-
- return true;
-}
-
-void dce80_transform_set_scaler(
- struct transform *xfm,
- const struct scaler_data *data)
-{
- struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- bool is_scaling_required;
- struct dc_context *ctx = xfm->ctx;
-
- dce80_transform_power_up_line_buffer(xfm);
-
- {
- uint32_t addr = SCL_REG(mmSCL_BYPASS_CONTROL);
- uint32_t value = dm_read_reg(xfm->ctx, addr);
-
- set_reg_field_value(
- value,
- 0,
- SCL_BYPASS_CONTROL,
- SCL_BYPASS_MODE);
- dm_write_reg(xfm->ctx, addr, value);
- }
-
- disable_enhanced_sharpness(xfm80);
-
- /* 3. Program overscan */
- program_overscan(xfm80, data);
-
- /* 4. Program taps and configuration */
- is_scaling_required = setup_scaling_configuration(xfm80, data);
- if (is_scaling_required) {
- /* 5. Calculate and program ratio, filter initialization */
- struct scl_ratios_inits inits = { 0 };
-
- calculate_inits(xfm80, data, &inits);
-
- program_scl_ratios_inits(xfm80, &inits);
-
- /* 6. Program vertical filters */
- if (data->taps.v_taps > 2) {
- program_two_taps_filter(xfm80, false, true);
-
- if (!program_multi_taps_filter(xfm80, data, false)) {
- dm_logger_write(ctx->logger, LOG_SCALER,
- "Failed vertical taps programming\n");
- return;
- }
- } else
- program_two_taps_filter(xfm80, true, true);
-
- /* 7. Program horizontal filters */
- if (data->taps.h_taps > 2) {
- program_two_taps_filter(xfm80, false, false);
-
- if (!program_multi_taps_filter(xfm80, data, true)) {
- dm_logger_write(ctx->logger, LOG_SCALER,
- "Failed horizontal taps programming\n");
- return;
- }
- } else
- program_two_taps_filter(xfm80, true, false);
- }
-
- /* 7. Program the viewport */
- program_viewport(xfm80, &data->viewport);
-}
--
2.10.1
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