[PATCH 6/7] drm/amd/dal: Program DPHY_SCRAM_CNTL for HBR2 compliance pattern

[Harry Wentland]

Change-Id: Ie76f6365870c47867dd3fb0b7346809adb4ed029
Signed-off-by: Harry Wentland <harry.wentland at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
---
 drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 7 +++++++
 drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h | 3 +++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index 5ca59fa8bcca..86e55d028cbf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -455,6 +455,9 @@ static void set_dp_phy_pattern_hbr2_compliance(
 
 	dal_write_reg(ctx, addr, value);
 	 */
+	/* swap every BS with SR */
+
+	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
 
 	/*TODO add support for this test pattern
 	 * support_dp_hbr2_eye_pattern
@@ -497,6 +500,8 @@ static void set_dp_phy_pattern_passthrough_mode(
 		REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
 	}
 
+	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
+
 	/* set link training complete */
 
 	set_link_training_complete(enc110, true);
@@ -543,6 +548,8 @@ static void configure_encoder(
 	REG_SET(DP_CONFIG, 0,
 			DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
 
+	/* setup scrambler */
+	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
 }
 
 static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h
index 463dbb5c34db..1635b239402f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h
@@ -61,6 +61,7 @@
 	SRI(DP_CONFIG, DP, id), \
 	SRI(DP_DPHY_CNTL, DP, id), \
 	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
+	SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
 	SRI(DP_DPHY_SYM0, DP, id), \
 	SRI(DP_DPHY_SYM1, DP, id), \
 	SRI(DP_DPHY_SYM2, DP, id), \
@@ -98,6 +99,7 @@
 		SR(BL1_PWM_USER_LEVEL), \
 		LE_COMMON_REG_LIST_BASE(id)
 
+
 struct dce110_link_enc_aux_registers {
 	uint32_t AUX_CONTROL;
 	uint32_t AUX_DPHY_RX_CONTROL0;
@@ -142,6 +144,7 @@ struct dce110_link_enc_registers {
 	uint32_t DP_DPHY_CNTL;
 	uint32_t DP_DPHY_INTERNAL_CTRL;
 	uint32_t DP_DPHY_PRBS_CNTL;
+	uint32_t DP_DPHY_SCRAM_CNTL;
 	uint32_t DP_DPHY_SYM0;
 	uint32_t DP_DPHY_SYM1;
 	uint32_t DP_DPHY_SYM2;
-- 
2.9.3