[PATCH] drm/amdgpu: cleanup VMHUB bit definitions v2
Deucher, Alexander
Alexander.Deucher at amd.com
Tue Apr 4 14:19:09 UTC 2017
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, April 04, 2017 9:20 AM
> To: amd-gfx at lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: cleanup VMHUB bit definitions v2
>
> From: Christian König <christian.koenig at amd.com>
>
> The two hubs are just instances of the same hardware,
> so the register bits are identical.
>
> v2: only remove get_vm_protection_bits for now
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 12 ------------
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 ++++++++----
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 12 ------------
> 4 files changed, 8 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index cc43fee..0c89e6b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -573,7 +573,6 @@ struct amdgpu_vmhub {
> uint32_t vm_l2_pro_fault_status;
> uint32_t vm_l2_pro_fault_cntl;
> uint32_t (*get_invalidate_req)(unsigned int vm_id);
> - uint32_t (*get_vm_protection_bits)(void);
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 30ef312..b808d4c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -318,17 +318,6 @@ static uint32_t
> gfxhub_v1_0_get_invalidate_req(unsigned int vm_id)
> return req;
> }
>
> -static uint32_t gfxhub_v1_0_get_vm_protection_bits(void)
> -{
> - return
> (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
> _MASK |
> -
> VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTE
> RRUPT_MASK |
> -
> VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_M
> ASK |
> -
> VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_
> MASK |
> -
> VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_M
> ASK |
> -
> VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_
> MASK |
> -
> VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT
> _MASK);
> -}
> -
> static int gfxhub_v1_0_early_init(void *handle)
> {
> return 0;
> @@ -362,7 +351,6 @@ static int gfxhub_v1_0_sw_init(void *handle)
> SOC15_REG_OFFSET(GC, 0,
> mmVM_L2_PROTECTION_FAULT_CNTL);
>
> hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req;
> - hub->get_vm_protection_bits =
> gfxhub_v1_0_get_vm_protection_bits;
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 268cedb..d813723 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -75,11 +75,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
> amdgpu_device *adev,
> struct amdgpu_vmhub *hub;
> u32 tmp, reg, bits, i;
>
> + bits =
> VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_
> MASK |
> +
> VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENAB
> LE_INTERRUPT_MASK |
> +
> VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERR
> UPT_MASK |
> +
> VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTER
> RUPT_MASK |
> +
> VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTER
> RUPT_MASK |
> +
> VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTER
> RUPT_MASK |
> +
> VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INT
> ERRUPT_MASK;
> +
> switch (state) {
> case AMDGPU_IRQ_STATE_DISABLE:
> /* MM HUB */
> hub = &adev->vmhub[AMDGPU_MMHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i< 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> @@ -89,7 +96,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
> amdgpu_device *adev,
>
> /* GFX HUB */
> hub = &adev->vmhub[AMDGPU_GFXHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i < 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> @@ -100,7 +106,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
> amdgpu_device *adev,
> case AMDGPU_IRQ_STATE_ENABLE:
> /* MM HUB */
> hub = &adev->vmhub[AMDGPU_MMHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i< 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> @@ -110,7 +115,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
> amdgpu_device *adev,
>
> /* GFX HUB */
> hub = &adev->vmhub[AMDGPU_GFXHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i < 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 266a0f4..a065b43 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -336,17 +336,6 @@ static uint32_t
> mmhub_v1_0_get_invalidate_req(unsigned int vm_id)
> return req;
> }
>
> -static uint32_t mmhub_v1_0_get_vm_protection_bits(void)
> -{
> - return
> (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
> _MASK |
> -
> VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTE
> RRUPT_MASK |
> -
> VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_M
> ASK |
> -
> VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_
> MASK |
> -
> VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_M
> ASK |
> -
> VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_
> MASK |
> -
> VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT
> _MASK);
> -}
> -
> static int mmhub_v1_0_early_init(void *handle)
> {
> return 0;
> @@ -380,7 +369,6 @@ static int mmhub_v1_0_sw_init(void *handle)
> SOC15_REG_OFFSET(MMHUB, 0,
> mmVM_L2_PROTECTION_FAULT_CNTL);
>
> hub->get_invalidate_req = mmhub_v1_0_get_invalidate_req;
> - hub->get_vm_protection_bits =
> mmhub_v1_0_get_vm_protection_bits;
>
> return 0;
> }
> --
> 2.5.0
>
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