[PATCH 2/2] drm/amd/amdgpu: Clean up psp reload_quirk()

[Alex Deucher]

On Tue, Apr 4, 2017 at 12:05 PM, Tom St Denis <tom.stdenis at amd.com> wrote:
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>

Series is:

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 0900fdf0651b..c3588d1c7cb0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -508,14 +508,10 @@ bool psp_v3_1_compare_sram_data(struct psp_context *psp,
>  bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
>  {
>         struct amdgpu_device *adev = psp->adev;
> -       uint32_t reg, reg_val;
> +       uint32_t reg;
>
> -       reg_val = (smnMP1_FIRMWARE_FLAGS & 0xffffffff) | 0x03b00000;
> -       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg_val);
> +       reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;
> +       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg);
>         reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2));
> -       if ((reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
> -            MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
> -               return true;
> -
> -       return false;
> +       return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
>  }
> --
> 2.12.0
>
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