[RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

[Andres Rodriguez]

On 2017-04-04 08:27 AM, Tom St Denis wrote:
> On 03/04/17 04:25 PM, Andres Rodriguez wrote:
>> Commit e579f56 results in a KCQ initialization error for polaris10
>> cards. Providing the full SET_RESOURCES packet instead of the truncated
>> version fixes the problem.
>>
>> I think this patch may have been one of the stabs at fixing the KCQ
>> suspend/resume errors. I *think* it may no longer be needed if that is
>> the case.
>>
>> Sending this mostly as an FYI to get the patch removed from the 4.12-wip
>>
>> This reverts commit e579f564c333a7eaddf7e12b1b8414410c36e80f.
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++++-
>>  1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> index 2d8d7bb..4c3bf51 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -4647,10 +4647,14 @@ static int gfx_v8_0_kiq_kcq_enable(struct
>> amdgpu_device *adev)
>>          return r;
>>      }
>>      /* set resources */
>> -    amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 2));
>> +    amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
>>      amdgpu_ring_write(kiq_ring, 0);    /* vmid_mask:0 queue_type:0
>> (KIQ) */
>>      amdgpu_ring_write(kiq_ring, 0x000000FF);    /* queue mask lo */
>>      amdgpu_ring_write(kiq_ring, 0);    /* queue mask hi */
>> +    amdgpu_ring_write(kiq_ring, 0);    /* gws mask lo */
>> +    amdgpu_ring_write(kiq_ring, 0);    /* gws mask hi */
>> +    amdgpu_ring_write(kiq_ring, 0);    /* oac mask */
>> +    amdgpu_ring_write(kiq_ring, 0);    /* gds heap base:0, gds heap
>> size:0 */
>>      for (i = 0; i < adev->gfx.num_compute_rings; i++) {
>>          struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
>>          uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
>>
>
> This fixes init issues with my polaris board but there's still a clock
> problem (CP is pegged at 100% as read by umr) resulting in the GPU clock
> staying at 1200MHz the entire time.
>

Yeah I sent this out because I was having KCQ init issues on my 
polaris10 card. However, I'm not seeing the CP pegged at 100% as you 
mentioned. Everything sitting quietly at 0% here.


> Tom
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