[PATCH 1/2] drm/amd/amdgpu: Introduce new read/write macros for SOC15

[Christian König]

Am 07.04.2017 um 13:55 schrieb Tom St Denis:
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>

A commit message would be nice, but either way Reviewed-by: Christian 
König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  3 ---
>   drivers/gpu/drm/amd/amdgpu/soc15_common.h | 20 +++++++++++++++++++-
>   2 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 548758063904..b7e7156dfa35 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1719,9 +1719,6 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
>   #define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
>   	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
>   
> -#define WREG32_FIELD15(ip, idx, reg, field, val)	\
> -	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
> -
>   /*
>    * BIOS helpers.
>    */
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index 2b96c806baa1..e8df6d820dbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -45,13 +45,31 @@ struct nbio_pcie_index_data {
>   	u32 index_offset;
>   	u32 data_offset;
>   };
> -// Register Access Macro
> +
> +/* Register Access Macros */
>   #define SOC15_REG_OFFSET(ip, inst, reg)       (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
>                                                   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
>                                                       (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
>                                                           (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>                                                               (ip##_BASE__INST##inst##_SEG4 + reg)))))
>   
> +#define WREG32_FIELD15(ip, idx, reg, field, val)	\
> +	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
> +
> +#define RREG32_SOC15(ip, inst, reg) \
> +	RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> +		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> +		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> +		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> +		(ip##_BASE__INST##inst##_SEG4 + reg))))))
> +
> +#define WREG32_SOC15(ip, inst, reg, value) \
> +	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> +		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> +		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> +		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> +		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> +
>   #endif
>   
>