[PATCH 3/3] drm/amdgpu: not set KIQ IRQ source in gfx_v9.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, April 18, 2017 3:02 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 3/3] drm/amdgpu: not set KIQ IRQ source in gfx_v9.
> 
> the system will trigger BUG_ON When amdgpu_fini is called,
> the IRQ source will be cleaned before IRQ uninstalled
> becasue of the sequence of ip_block.
> so not set irq source.
> 
> Change-Id: I64b99247c36edb84bd209905eb24b391720b4d8f
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

I think Trigger sent the same patch.  Either one is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++--------
>  1 file changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f6b2329..84b31a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -631,7 +631,6 @@ static int gfx_v9_0_kiq_init_ring(struct
> amdgpu_device *adev,
>  		ring->pipe = 1;
>  	}
> 
> -	irq->data = ring;
>  	ring->queue = 0;
>  	ring->eop_gpu_addr = kiq->eop_gpu_addr;
>  	sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring-
> >queue);
> @@ -647,7 +646,6 @@ static void gfx_v9_0_kiq_free_ring(struct
> amdgpu_ring *ring,
>  {
>  	amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
>  	amdgpu_ring_fini(ring);
> -	irq->data = NULL;
>  }
> 
>  /* create MQD for each compute queue */
> @@ -3367,9 +3365,7 @@ static int gfx_v9_0_kiq_set_interrupt_state(struct
> amdgpu_device *adev,
>  					    enum amdgpu_interrupt_state
> state)
>  {
>  	uint32_t tmp, target;
> -	struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data;
> -
> -	BUG_ON(!ring || (ring->funcs->type !=
> AMDGPU_RING_TYPE_KIQ));
> +	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
> 
>  	if (ring->me == 1)
>  		target = SOC15_REG_OFFSET(GC, 0,
> mmCP_ME1_PIPE0_INT_CNTL);
> @@ -3413,9 +3409,7 @@ static int gfx_v9_0_kiq_irq(struct amdgpu_device
> *adev,
>  			    struct amdgpu_iv_entry *entry)
>  {
>  	u8 me_id, pipe_id, queue_id;
> -	struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data;
> -
> -	BUG_ON(!ring || (ring->funcs->type !=
> AMDGPU_RING_TYPE_KIQ));
> +	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
> 
>  	me_id = (entry->ring_id & 0x0c) >> 2;
>  	pipe_id = (entry->ring_id & 0x03) >> 0;
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx