[PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

[Tom St Denis]

On 18/04/17 01:00 PM, Andres Rodriguez wrote:

>> +static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
>> +{
>> +    struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
>> +    uint32_t scratch, tmp = 0;
>> +    int r, i;
>> +
>> +    r = amdgpu_gfx_scratch_get(adev, &scratch);
>> +    if (r) {
>> +        DRM_ERROR("Failed to get scratch reg (%d).\n", r);
>> +        return r;
>> +    }
>> +    WREG32(scratch, 0xCAFEDEAD);
> 
> WREG32_SOC15 needed here I think

In the function gfx_v9_0_scratch_init() the offset is initialized with 
GC/0 using a SOC15 macro.  After that you can use normal WREG32/RREG32 
on it.

Tom