[PATCH 04/11] drm/amdgpu/vce4: fix a PSP loading VCE issue

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Xiangliang Yu
> Sent: Monday, April 24, 2017 2:58 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Wang, Daniel(Xiaowei); Yu, Xiangliang
> Subject: [PATCH 04/11] drm/amdgpu/vce4: fix a PSP loading VCE issue
> 
> From: Daniel Wang <Daniel.Wang2 at amd.com>
> 
> Fixed PSP loading issue for sriov.
> 
> Signed-off-by: Daniel Wang <Daniel.Wang2 at amd.com>
> Signed-off-by: Xiangliang Yu <Xiangliang.Yu at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 76fc8ed..1deb546 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -291,9 +291,21 @@ static int vce_v4_0_sriov_start(struct
> amdgpu_device *adev)
>  		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_SWAP_CNTL1), 0);
>  		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VM_CTRL), 0);
> 
> -		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->vce.gpu_addr >> 8);
> -		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), adev->vce.gpu_addr >> 8);
> -		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), adev->vce.gpu_addr >> 8);
> +		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> {
> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> +				adev-
> >firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> +				adev-
> >firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +				adev-
> >firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> +		} else {
> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> +				adev->vce.gpu_addr >> 8);
> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> +				adev->vce.gpu_addr >> 8);
> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +				adev->vce.gpu_addr >> 8);
> +		}
> 
>  		offset = AMDGPU_VCE_FIRMWARE_OFFSET;
>  		size = VCE_V4_0_FW_SIZE;
> --
> 2.7.4
> 
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