[PATCH] drm/amdgpu: update vega10/raven gc/sdma golden setting logic to change only AndMasked bits

[Evan Quan]

Change-Id: I378f29341816e0e026ae42e818860e69eec0f029
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      |  8 ++++----
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     |  8 ++++----
 4 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c737768..8f0c63f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1892,6 +1892,9 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev);
 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 					     const u32 *registers,
 					     const u32 array_size);
+void amdgpu_program_register_sequence_andmasked_bits(struct amdgpu_device *adev,
+					     const u32 *registers,
+					     const u32 array_size);
 
 bool amdgpu_device_is_px(struct drm_device *dev);
 /* atpx handler */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e512f98..ab6cebe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -385,6 +385,32 @@ void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 	}
 }
 
+void amdgpu_program_register_sequence_andmasked_bits(struct amdgpu_device *adev,
+				      const u32 *registers,
+				      const u32 array_size)
+{
+	u32 tmp, reg, and_mask, or_mask;
+	int i;
+
+	if (array_size % 3)
+		return;
+
+	for (i = 0; i < array_size; i +=3) {
+		reg = registers[i + 0];
+		and_mask = registers[i + 1];
+		or_mask = registers[i + 2];
+
+		if (and_mask == 0xffffffff) {
+			tmp = or_mask;
+		} else {
+			tmp = RREG32(reg);
+			tmp &= ~and_mask;
+			tmp |= (and_mask & or_mask);
+		}
+		WREG32(reg, tmp);
+	}
+}
+
 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 {
 	pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 59cdd54..dcbf166 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -191,18 +191,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_gc_9_0,
 						 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_gc_9_0_vg10,
 						 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 		break;
 	case CHIP_RAVEN:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_gc_9_1,
 						 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_gc_9_1_rv1,
 						 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fd7c72a..ce9edca 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -130,18 +130,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_sdma_4,
 						 (const u32)ARRAY_SIZE(golden_settings_sdma_4));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_sdma_vg10,
 						 (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
 		break;
 	case CHIP_RAVEN:
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_sdma_4_1,
 						 (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
-		amdgpu_program_register_sequence(adev,
+		amdgpu_program_register_sequence_andmasked_bits(adev,
 						 golden_settings_sdma_rv1,
 						 (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
 		break;
-- 
2.7.4