[PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test

[Ken Wang]

Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
Signed-off-by: Ken Wang <Ken.Wang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 68a0d40..66312d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1670,6 +1670,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
 	u32 tmp;
 	u32 rb_bufsz;
 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
+	int r;
 
 	/* Set the write pointer delay */
 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
@@ -1729,6 +1730,17 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
 
 	/* start the ring */
 	gfx_v9_0_cp_gfx_start(adev);
+
+	r = amdgpu_ring_alloc(ring, 3);
+	if (r) {
+		return r;
+	}
+	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+	tmp = ((2 << 28) | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
+	amdgpu_ring_write(ring, tmp);
+	amdgpu_ring_write(ring, 0);
+	amdgpu_ring_commit(ring);
+
 	ring->ready = true;
 
 	return 0;
-- 
2.7.4