[PATCH] drm/amd/amdgpu: fix BANK_SELECT on Vega10

[Christian König]

Am 24.08.2017 um 09:07 schrieb Roger He:
> BANK_SELECT should always be FRAGMENT_SIZE + 3 due to 8-entry (2^3)
> per cache line in L2 TLB for Vega10.
>
> Change-Id: I8cfcff197e2c571c1a547aaed959e492b4a6fe0e
> Signed-off-by: Roger He <Hongbo.He at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 3 +--
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 3 +--
>   2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 4f2788b..a7351ba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -143,9 +143,8 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>   	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
>   	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
>   
> -	field = adev->vm_manager.fragment_size;
>   	tmp = mmVM_L2_CNTL3_DEFAULT;
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
> +	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
>   	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
>   	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 4395a4f..2a6fa73 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -157,9 +157,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>   	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
>   	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
>   
> -	field = adev->vm_manager.fragment_size;
>   	tmp = mmVM_L2_CNTL3_DEFAULT;
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
> +	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
>   	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
>   	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
>