[PATCH 03/14] drm/amd/amdgpu: Tidy up gfx_v9_0_gpu_init()

[Tom St Denis]

On 31/08/17 12:27 PM, Alex Deucher wrote:
> On Thu, Aug 31, 2017 at 12:06 PM, Tom St Denis <tom.stdenis at amd.com> wrote:
>> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++----------
>>   1 file changed, 3 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 99cd10eceea9..53ef3769df0c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -1531,13 +1531,11 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
>>
>>   static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
>>   {
>> -       u32 tmp;
>>          int i;
>>
>>          WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
>>
>>          gfx_v9_0_tiling_mode_table_init(adev);
>> -
>>          gfx_v9_0_setup_rb(adev);
>>          gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
>>
>> @@ -1547,25 +1545,21 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
>>          for (i = 0; i < 16; i++) {
>>                  soc15_grbm_select(adev, 0, 0, 0, i);
>>                  /* CP and shaders */
>> -               tmp = 0;
>> -               tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
>> -                                   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
>> -               WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
>> +               WREG32_FIELD15(GC, 0, SH_MEM_CONFIG, ALIGNMENT_MODE,
>> +                              SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> 
> There is a slight change in behavior here.  Previously we were setting
> the entire register to 0 except the alignment mode.  now we just
> change the alignment mode.  It's probably more correct as you've
> written it and the default value of the register is 0 anyway, but it
> is a change.  Probably worth splitting this out as a separate change.

I'll just remove this from this series since the intent was no real 
functional changes.  I'll then add on a two patch change after to clean 
this up.

Thanks,
Tom

> 
> Alex
> 
>>                  WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
>>          }
>>          soc15_grbm_select(adev, 0, 0, 0, 0);
>> -
>>          mutex_unlock(&adev->srbm_mutex);
>>
>>          gfx_v9_0_init_compute_vmid(adev);
>>
>> -       mutex_lock(&adev->grbm_idx_mutex);
>>          /*
>>           * making sure that the following register writes will be broadcasted
>>           * to all the shaders
>>           */
>> +       mutex_lock(&adev->grbm_idx_mutex);
>>          gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
>> -
>>          WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
>>                     (adev->gfx.config.sc_prim_fifo_size_frontend <<
>>                          PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
>> @@ -1576,7 +1570,6 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
>>                     (adev->gfx.config.sc_earlyz_tile_fifo_size <<
>>                          PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
>>          mutex_unlock(&adev->grbm_idx_mutex);
>> -
>>   }
>>
>>   static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
>> --
>> 2.12.0
>>
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