[PATCH 65/77] drm/amd/display: Fix time out on boot
Harry Wentland
harry.wentland at amd.com
Thu Aug 31 18:09:00 UTC 2017
From: Eric Yang <Eric.Yang2 at amd.com>
On boot, hubp 0 is powergated during enable accel mode, so we time out
when we try to blank in undo wa.
Fix: Check power gate status before set blank
Change-Id: Ia14455722e5a8b6136d47083f1986827ed07175a
Signed-off-by: Eric Yang <Eric.Yang2 at amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 71ff1cedbdf4..7ea274475598 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -780,6 +780,12 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
{
struct dce_hwseq *hws = dc->hwseq;
struct mem_input *mi = dc->res_pool->mis[0];
+ int pwr_status = 0;
+
+ REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status);
+ /* Don't need to blank if hubp is power gated*/
+ if (pwr_status == 2)
+ return;
mi->funcs->set_blank(mi, true);
--
2.11.0
More information about the amd-gfx
mailing list