[PATCH 5/5] drm/amd/pp: implement force_dpm_level on rv
Alex Deucher
alexdeucher at gmail.com
Mon Dec 18 17:03:26 UTC 2017
On Mon, Dec 18, 2017 at 6:50 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> user can change engine/mclk/soc/vcn clocks on Rv
>
> v3: add smu version check
> v2: fix no return statement
>
> Change-Id: I4cba759701ab031085a687102de6566771f4494f
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
Patches 1-4:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 127 +++++++++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 15 +++
> 2 files changed, 142 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index ae11a85..91f1912 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -484,6 +484,133 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
> static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> enum amd_dpm_forced_level level)
> {
> + uint32_t version;
> +
> + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
> + rv_read_arg_from_smc(hwmgr, &version);
> + if (version < 0x1E3700) {
> + pr_info("smu firmware version too old, can not set dpm level\n");
> + return 0;
> + }
I think it would be better to store this in hwmgr state than to look
it up every time. We need to add fetch it earlier anyway so that we
export the smu version on APUs properly so we can fix the SMU fw
version we expose to userspace (rather than always reporting 0 for
APUs).
Alex
> +
> + switch (level) {
> + case AMD_DPM_FORCED_LEVEL_HIGH:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinSocclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinVcn,
> + RAVEN_UMD_PSTATE_VCE);
> +
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxSocclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxVcn,
> + RAVEN_UMD_PSTATE_VCE);
> + break;
> + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + break;
> + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + break;
> + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinSocclkByFreq,
> + RAVEN_UMD_PSTATE_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinVcn,
> + RAVEN_UMD_PSTATE_VCE);
> +
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxSocclkByFreq,
> + RAVEN_UMD_PSTATE_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxVcn,
> + RAVEN_UMD_PSTATE_VCE);
> + break;
> + case AMD_DPM_FORCED_LEVEL_AUTO:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinSocclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinVcn,
> + RAVEN_UMD_PSTATE_MIN_VCE);
> +
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxSocclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxVcn,
> + RAVEN_UMD_PSTATE_VCE);
> + break;
> + case AMD_DPM_FORCED_LEVEL_LOW:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + break;
> + case AMD_DPM_FORCED_LEVEL_MANUAL:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> + default:
> + break;
> + }
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> index 9dc5030..c3bc311 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> @@ -304,4 +304,19 @@ struct rv_hwmgr {
>
> int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
>
> +/* UMD PState Raven Msg Parameters in MHz */
> +#define RAVEN_UMD_PSTATE_GFXCLK 700
> +#define RAVEN_UMD_PSTATE_SOCCLK 626
> +#define RAVEN_UMD_PSTATE_FCLK 933
> +#define RAVEN_UMD_PSTATE_VCE 0x03C00320
> +
> +#define RAVEN_UMD_PSTATE_PEAK_GFXCLK 1100
> +#define RAVEN_UMD_PSTATE_PEAK_SOCCLK 757
> +#define RAVEN_UMD_PSTATE_PEAK_FCLK 1200
> +
> +#define RAVEN_UMD_PSTATE_MIN_GFXCLK 200
> +#define RAVEN_UMD_PSTATE_MIN_FCLK 400
> +#define RAVEN_UMD_PSTATE_MIN_SOCCLK 200
> +#define RAVEN_UMD_PSTATE_MIN_VCE 0x0190012C
> +
> #endif
> --
> 1.9.1
>
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