[PATCH 1/2] drm/amdgpu: only check mmBIF_IOV_FUNC_IDENTIFIER on tonga/fiji
Yu, Xiangliang
Xiangliang.Yu at amd.com
Wed Dec 20 02:33:18 UTC 2017
Reviewed-by: Xiangliang Yu <Xiangliang.Yu at amd.com>
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Alex Deucher
> Sent: Tuesday, December 19, 2017 11:07 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
> Subject: [PATCH 1/2] drm/amdgpu: only check
> mmBIF_IOV_FUNC_IDENTIFIER on tonga/fiji
>
> We only support SR-IOV on tonga/fiji. Don't check this register on other VI
> parts.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vi.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
> b/drivers/gpu/drm/amd/amdgpu/vi.c index d9bb26322850..c59b37365e4d
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -449,14 +449,19 @@ static bool vi_read_bios_from_rom(struct
> amdgpu_device *adev,
>
> static void vi_detect_hw_virtualization(struct amdgpu_device *adev) {
> - uint32_t reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
> - /* bit0: 0 means pf and 1 means vf */
> - /* bit31: 0 means disable IOV and 1 means enable */
> - if (reg & 1)
> - adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
> -
> - if (reg & 0x80000000)
> - adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
> + uint32_t reg = 0;
> +
> + if (adev->asic_type == CHIP_TONGA ||
> + adev->asic_type == CHIP_FIJI) {
> + reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
> + /* bit0: 0 means pf and 1 means vf */
> + /* bit31: 0 means disable IOV and 1 means enable */
> + if (reg & 1)
> + adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
> +
> + if (reg & 0x80000000)
> + adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
> + }
>
> if (reg == 0) {
> if (is_virtual_machine()) /* passthrough mode exclus sr-iov
> mode */
> --
> 2.13.6
>
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