[PATCH] drm/amdgpu: Initialize pipe priority order on graphic initialization

[Alex Deucher]

On Fri, Feb 10, 2017 at 7:27 PM, ozeng <zengshanjun at gmail.com> wrote:
> Initialized PIPE_ORDER_TS0/1/2/3 field of SPI_ARB_PRIORITY register to 2.
> This set the pipe priority order to:
> 02 - HP3D, CS_H, GFX, CS_M, CS_L
>
> Change-Id: I1e89a2fdcf45a99808f0f5b3cbd83ae537174023
> Signed-off-by: Oak Zeng <Oak.Zeng at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>


> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 ++++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 ++++++++
>  2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 8dcb929..e9d6344 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -1983,6 +1983,14 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
>         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
>                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
>         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
> +
> +       tmp = RREG32(mmSPI_ARB_PRIORITY);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
> +       WREG32(mmSPI_ARB_PRIORITY, tmp);
> +
>         mutex_unlock(&adev->grbm_idx_mutex);
>
>         udelay(50);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 9542fed..772c42b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3905,6 +3905,14 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
>                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
>                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
>                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
> +
> +       tmp = RREG32(mmSPI_ARB_PRIORITY);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
> +       tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
> +       WREG32(mmSPI_ARB_PRIORITY, tmp);
> +
>         mutex_unlock(&adev->grbm_idx_mutex);
>
>  }
> --
> 2.7.4
>
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