[PATCH 09/25] drm/amd/display: remove un-used defines and dead code
Harry Wentland
harry.wentland at amd.com
Mon Jan 23 14:35:57 UTC 2017
From: Tony Cheng <tony.cheng at amd.com>
Change-Id: Ib32be9d265062d862557568b19160d7a866bb454
Signed-off-by: Tony Cheng <tony.cheng at amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland at amd.com>
---
.../gpu/drm/amd/display/dc/basics/signal_types.c | 35 -------
.../gpu/drm/amd/display/dc/bios/command_table.c | 55 ----------
.../gpu/drm/amd/display/dc/bios/command_table.h | 3 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 -
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
.../display/include/asic_capability_interface.h | 55 ----------
.../amd/display/include/asic_capability_types.h | 116 ---------------------
.../drm/amd/display/include/bios_parser_types.h | 8 --
.../drm/amd/display/include/ddc_service_types.h | 7 --
.../gpu/drm/amd/display/include/irq_interface.h | 31 ------
.../drm/amd/display/include/link_service_types.h | 75 -------------
drivers/gpu/drm/amd/display/include/signal_types.h | 3 -
12 files changed, 1 insertion(+), 390 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/include/asic_capability_interface.h
delete mode 100644 drivers/gpu/drm/amd/display/include/asic_capability_types.h
delete mode 100644 drivers/gpu/drm/amd/display/include/irq_interface.h
diff --git a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c b/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
index 44447e07803a..247487c3db71 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/signal_types.c
@@ -44,23 +44,6 @@ bool dc_is_dp_signal(enum signal_type signal)
signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
}
-bool dc_is_dp_external_signal(enum signal_type signal)
-{
- return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
- signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-}
-
-bool dc_is_analog_signal(enum signal_type signal)
-{
- switch (signal) {
- case SIGNAL_TYPE_RGB:
- return true;
- break;
- default:
- return false;
- }
-}
-
bool dc_is_embedded_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_EDP || signal == SIGNAL_TYPE_LVDS);
@@ -96,21 +79,3 @@ bool dc_is_audio_capable_signal(enum signal_type signal)
signal == SIGNAL_TYPE_WIRELESS);
}
-/*
- * @brief
- * Returns whether the signal is compatible
- * with other digital encoder signal types.
- * This is true for DVI, LVDS, and HDMI signal types.
- */
-bool dc_is_digital_encoder_compatible_signal(enum signal_type signal)
-{
- switch (signal) {
- case SIGNAL_TYPE_DVI_SINGLE_LINK:
- case SIGNAL_TYPE_DVI_DUAL_LINK:
- case SIGNAL_TYPE_HDMI_TYPE_A:
- case SIGNAL_TYPE_LVDS:
- return true;
- default:
- return false;
- }
-}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index d0eedb6235fe..88aaf53cb8c4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -56,7 +56,6 @@ static void init_dac_encoder_control(struct bios_parser *bp);
static void init_dac_output_control(struct bios_parser *bp);
static void init_blank_crtc(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
-static void init_set_crtc_overscan(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_enable_crtc_mem_req(struct bios_parser *bp);
@@ -77,7 +76,6 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_dac_output_control(bp);
init_blank_crtc(bp);
init_set_crtc_timing(bp);
- init_set_crtc_overscan(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_enable_crtc_mem_req(bp);
@@ -1934,59 +1932,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
/*******************************************************************************
********************************************************************************
**
- ** SET CRTC OVERSCAN
- **
- ********************************************************************************
- *******************************************************************************/
-
-static enum bp_result set_crtc_overscan_v1(
- struct bios_parser *bp,
- struct bp_hw_crtc_overscan_parameters *bp_params);
-
-static void init_set_crtc_overscan(struct bios_parser *bp)
-{
- switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_OverScan)) {
- case 1:
- bp->cmd_tbl.set_crtc_overscan = set_crtc_overscan_v1;
- break;
- default:
- bp->cmd_tbl.set_crtc_overscan = NULL;
- break;
- }
-}
-
-static enum bp_result set_crtc_overscan_v1(
- struct bios_parser *bp,
- struct bp_hw_crtc_overscan_parameters *bp_params)
-{
- enum bp_result result = BP_RESULT_FAILURE;
- SET_CRTC_OVERSCAN_PARAMETERS params = {0};
- uint8_t atom_controller_id;
-
- if (bp->cmd_helper->controller_id_to_atom(
- bp_params->controller_id, &atom_controller_id))
- params.ucCRTC = atom_controller_id;
- else
- return BP_RESULT_BADINPUT;
-
- params.usOverscanRight =
- cpu_to_le16((uint16_t)bp_params->h_overscan_right);
- params.usOverscanLeft =
- cpu_to_le16((uint16_t)bp_params->h_overscan_left);
- params.usOverscanBottom =
- cpu_to_le16((uint16_t)bp_params->v_overscan_bottom);
- params.usOverscanTop =
- cpu_to_le16((uint16_t)bp_params->v_overscan_top);
-
- if (EXEC_BIOS_CMD_TABLE(SetCRTC_OverScan, params))
- result = BP_RESULT_OK;
-
- return result;
-}
-
-/*******************************************************************************
- ********************************************************************************
- **
** SELECT CRTC SOURCE
**
********************************************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.h b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
index e1cd21b6e968..b8e6ef06c0c7 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
@@ -75,9 +75,6 @@ struct cmd_tbl {
enum bp_result (*set_crtc_timing)(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params);
- enum bp_result (*set_crtc_overscan)(
- struct bios_parser *bp,
- struct bp_hw_crtc_overscan_parameters *bp_params);
enum bp_result (*select_crtc_source)(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b0f316344e86..62cfc5cbe773 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -38,7 +38,6 @@
#include "hw_sequencer.h"
#include "resource.h"
#include "fixed31_32.h"
-#include "include/asic_capability_interface.h"
#include "dpcd_defs.h"
#include "dce/dce_11_0_d.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 3d5871dfc8e6..bc0667d55cf0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1922,7 +1922,7 @@ static void get_active_converter_info(
break;
}
- if (link->dpcd_caps.dpcd_rev.raw >= DCS_DPCD_REV_11) {
+ if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
uint8_t det_caps[4];
union dwnstream_port_caps_byte0 *port_caps =
(union dwnstream_port_caps_byte0 *)det_caps;
diff --git a/drivers/gpu/drm/amd/display/include/asic_capability_interface.h b/drivers/gpu/drm/amd/display/include/asic_capability_interface.h
deleted file mode 100644
index 57cc72fdc560..000000000000
--- a/drivers/gpu/drm/amd/display/include/asic_capability_interface.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of enc software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and enc permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_ASIC_CAPABILITY_INTERFACE_H__
-#define __DAL_ASIC_CAPABILITY_INTERFACE_H__
-
-/* Include */
-#include "include/asic_capability_types.h"
-
-/* Forward declaration */
-struct hw_asic_id;
-
-/* ASIC capability */
-struct asic_capability {
- struct dc_context *ctx;
- struct asic_caps caps;
- struct asic_stereo_3d_caps stereo_3d_caps;
- struct asic_bugs bugs;
- uint32_t data[ASIC_DATA_MAX_NUMBER];
-};
-
-/**
- * Interfaces
- */
-
-/* Create and initialize ASIC capability */
-struct asic_capability *dal_asic_capability_create(struct hw_asic_id *init,
- struct dc_context *ctx);
-
-/* Destroy ASIC capability and free memory space */
-void dal_asic_capability_destroy(struct asic_capability **cap);
-
-#endif /* __DAL_ASIC_CAPABILITY_INTERFACE_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/asic_capability_types.h b/drivers/gpu/drm/amd/display/include/asic_capability_types.h
deleted file mode 100644
index c44dae043599..000000000000
--- a/drivers/gpu/drm/amd/display/include/asic_capability_types.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#ifndef __DAL_ASIC_CAPABILITY_TYPES_H__
-#define __DAL_ASIC_CAPABILITY_TYPES_H__
-
-/*
- * ASIC Capabilities
- */
-struct asic_caps {
- bool CONSUMER_SINGLE_SELECTED_TIMING:1;
- bool UNDERSCAN_ADJUST:1;
- bool DELTA_SIGMA_SUPPORT:1;
- bool PANEL_SELF_REFRESH_SUPPORTED:1;
- bool IS_FUSION:1;
- bool DP_MST_SUPPORTED:1;
- bool UNDERSCAN_FOR_HDMI_ONLY:1;
- bool DVI_CLOCK_SHARE_CAPABILITY:1;
- bool SUPPORT_CEA861E_FINAL:1;
- bool MIRABILIS_SUPPORTED:1;
- bool MIRABILIS_ENABLED_BY_DEFAULT:1;
- bool DEVICE_TAG_REMAP_SUPPORTED:1;
- bool HEADLESS_NO_OPM_SUPPORTED:1;
- bool WIRELESS_LIMIT_TO_720P:1;
- bool WIRELESS_FULL_TIMING_ADJUSTMENT:1;
- bool WIRELESS_TIMING_ADJUSTMENT:1;
- bool WIRELESS_COMPRESSED_AUDIO:1;
- bool VCE_SUPPORTED:1;
- bool HPD_CHECK_FOR_EDID:1;
- bool NEED_MC_TUNING:1;
- bool SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT:1;
- bool DFSBYPASS_DYNAMIC_SUPPORT:1;
- bool SUPPORT_8BPP:1;
-};
-
-/*
- * ASIC Stereo 3D Caps
- */
-struct asic_stereo_3d_caps {
- bool SUPPORTED:1;
- bool DISPLAY_BASED_ON_WS:1;
- bool HDMI_FRAME_PACK:1;
- bool INTERLACE_FRAME_PACK:1;
- bool DISPLAYPORT_FRAME_PACK:1;
- bool DISPLAYPORT_FRAME_ALT:1;
- bool INTERLEAVE:1;
-};
-
-/*
- * ASIC Bugs
- */
-struct asic_bugs {
- bool MST_SYMBOL_MISALIGNMENT:1;
- bool PSR_2X_LANE_GANGING:1;
- bool LB_WA_IS_SUPPORTED:1;
- bool ROM_REGISTER_ACCESS:1;
- bool PSR_WA_OVERSCAN_CRC_ERROR:1;
-};
-
-/*
- * ASIC Data
- */
-enum asic_data {
- ASIC_DATA_FIRST = 0,
- ASIC_DATA_DCE_VERSION = ASIC_DATA_FIRST,
- ASIC_DATA_DCE_VERSION_MINOR,
- ASIC_DATA_LINEBUFFER_SIZE,
- ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY,
- ASIC_DATA_MC_LATENCY,
- ASIC_DATA_MC_LATENCY_SLOW,
- ASIC_DATA_MEMORYTYPE_MULTIPLIER,
- ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR,
- ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
- ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
- ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN,
- ASIC_DATA_DOWNSCALE_LIMIT,
- ASIC_DATA_MAX_NUMBER /* end of enum */
-};
-
-/*
- * ASIC Feature Flags
- */
-struct asic_feature_flags {
- union {
- uint32_t raw;
- struct {
- uint32_t LEGACY_CLIENT:1;
- uint32_t PACKED_PIXEL_FORMAT:1;
- uint32_t WORKSTATION_STEREO:1;
- uint32_t WORKSTATION:1;
- } bits;
- };
-};
-
-#endif /* __DAL_ASIC_CAPABILITY_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index 9ab9065735f7..7de4fa5a0726 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -190,14 +190,6 @@ struct bp_hw_crtc_timing_parameters {
} flags;
};
-struct bp_hw_crtc_overscan_parameters {
- enum controller_id controller_id;
- uint32_t h_overscan_left;
- uint32_t h_overscan_right;
- uint32_t v_overscan_top;
- uint32_t v_overscan_bottom;
-};
-
struct bp_adjust_pixel_clock_parameters {
/* Input: Signal Type - to be converted to Encoder mode */
enum signal_type signal_type;
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 0a6ba91e3eba..effe03b8f418 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -52,12 +52,6 @@ enum ddc_service_type {
DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
};
-enum dcs_dpcd_revision {
- DCS_DPCD_REV_10 = 0x10,
- DCS_DPCD_REV_11 = 0x11,
- DCS_DPCD_REV_12 = 0x12
-};
-
/**
* display sink capability
*/
@@ -97,7 +91,6 @@ struct display_sink_capability {
uint32_t dp_link_rate;
uint32_t dp_link_spead;
- enum dcs_dpcd_revision dpcd_revision;
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
bool is_dp_hdmi_s3d_converter;
diff --git a/drivers/gpu/drm/amd/display/include/irq_interface.h b/drivers/gpu/drm/amd/display/include/irq_interface.h
deleted file mode 100644
index 077ded3fbedd..000000000000
--- a/drivers/gpu/drm/amd/display/include/irq_interface.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_IRQ_INTERFACE_H__
-#define __DAL_IRQ_INTERFACE_H__
-
-#include "gpio_types.h"
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 6160a467ba37..479e5fff8a00 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -38,34 +38,11 @@ enum {
MAX_CONTROLLER_NUM = 6
};
-enum link_service_type {
- LINK_SERVICE_TYPE_LEGACY = 0,
- LINK_SERVICE_TYPE_DP_SST,
- LINK_SERVICE_TYPE_DP_MST,
- LINK_SERVICE_TYPE_MAX
-};
-
-enum dpcd_value_mask {
- DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F,
- DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40,
- DPCD_VALUE_MASK_MAX_LANE_COUNT_ENHANCED_FRAME_EN = 0x80,
- DPCD_VALUE_MASK_MAX_DOWNSPREAD = 0x01,
- DPCD_VALUE_MASK_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE = 0x01
-};
-
enum dp_power_state {
DP_POWER_STATE_D0 = 1,
DP_POWER_STATE_D3
};
-enum dpcd_downstream_port_types {
- DPCD_DOWNSTREAM_DP,
- DPCD_DOWNSTREAM_VGA,
- DPCD_DOWNSTREAM_DVI_HDMI,
- /* has no EDID (TV, CV) */
- DPCD_DOWNSTREAM_NON_DDC
-};
-
enum edp_revision {
/* eDP version 1.1 or lower */
EDP_REVISION_11 = 0x00,
@@ -135,36 +112,6 @@ enum dp_panel_mode {
DP_PANEL_MODE_SPECIAL
};
-/**
- * @brief LinkServiceInitOptions to set certain bits
- */
-struct link_service_init_options {
- uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1;
-};
-
-/**
- * @brief data required to initialize LinkService
- */
-struct link_service_init_data {
- /* number of displays indices which the MST Mgr would manange*/
- uint32_t num_of_displays;
- enum link_service_type link_type;
- /*struct mst_mgr_callback_object*topology_change_callback;*/
- /* native aux access */
- struct ddc_service *dpcd_access_srv;
- /* for calling HWSS to program HW */
- struct hw_sequencer *hwss;
- /* the source which to register IRQ on */
- enum dc_irq_source irq_src_hpd_rx;
- enum dc_irq_source irq_src_dp_sink;
- /* other init options such as SW Workarounds */
- struct link_service_init_options init_options;
- uint32_t connector_enum_id;
- struct graphics_object_id connector_id;
- struct dc_context *ctx;
- struct topology_mgr *tm;
-};
-
/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
union dpcd_training_lane_set {
struct {
@@ -189,28 +136,6 @@ union dpcd_training_lane_set {
uint8_t raw;
};
-/**
- * @brief represent the 16 byte
- * global unique identifier
- */
-struct mst_guid {
- uint8_t ids[16];
-};
-
-/**
- * @brief represents the relative address used
- * to identify a node in MST topology network
- */
-struct mst_rad {
- /* number of links. rad[0] up to
- * rad [linkCount - 1] are valid. */
- uint32_t rad_link_count;
- /* relative address. rad[0] is the
- * first device connected to the source. */
- uint8_t rad[15];
- /* extra 10 bytes for underscores; for e.g.:2_1_8*/
- int8_t rad_str[25];
-};
/* DP MST stream allocation (payload bandwidth number) */
struct dp_mst_stream_allocation {
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h
index a50f7ed74a33..d87f84a56fcc 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -47,13 +47,10 @@ enum signal_type {
bool dc_is_hdmi_signal(enum signal_type signal);
bool dc_is_dp_sst_signal(enum signal_type signal);
bool dc_is_dp_signal(enum signal_type signal);
-bool dc_is_dp_external_signal(enum signal_type signal);
-bool dc_is_analog_signal(enum signal_type signal);
bool dc_is_embedded_signal(enum signal_type signal);
bool dc_is_dvi_signal(enum signal_type signal);
bool dc_is_dvi_single_link_signal(enum signal_type signal);
bool dc_is_dual_link_signal(enum signal_type signal);
bool dc_is_audio_capable_signal(enum signal_type signal);
-bool dc_is_digital_encoder_compatible_signal(enum signal_type signal);
#endif
--
2.9.3
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