[PATCH 4/6] drm/amdgpu: implement PRT for GFX6

[StDenis, Tom]

Minor nit: the comment says v8 [😊]


The changes to the GFX6/7/8 look reasonable though only question is you read from mmVM_PRT_CNTL and then write to mmVM_CONTEXT1_CNTL .  Is that expected?


Tom


________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Christian König <deathsimple at vodafone.de>
Sent: Monday, January 30, 2017 07:57
To: bas at basnieuwenhuizen.nl; airlied at gmail.com
Cc: amd-gfx at lists.freedesktop.org
Subject: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6

From: Christian König <christian.koenig at amd.com>

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

Signed-off-by: Christian König <christian.koenig at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 63 +++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index e2b0b16..c23503e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,68 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }

+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+       u32 tmp;
+
+       if (enable && !adev->mc.prt_warning) {
+               dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
+               adev->mc.prt_warning = true;
+       }
+
+       tmp = RREG32(mmVM_PRT_CNTL);
+       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+                           CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+                           enable);
+       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+                           CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+                           enable);
+       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+                           TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,
+                           enable);
+       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+                           TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,
+                           enable);
+       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+                           L2_CACHE_STORE_INVALID_ENTRIES,
+                           enable);
+       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+                           L1_TLB_STORE_INVALID_ENTRIES,
+                           enable);
+       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+                           MASK_PDE0_FAULT, enable);
+       WREG32(mmVM_CONTEXT1_CNTL, tmp);
+
+       if (enable) {
+               uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+               uint32_t high = adev->vm_manager.max_pfn;
+
+               WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+               WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+               WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+               WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+               WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+               WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+               WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+               WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+       } else {
+               WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
+               WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
+               WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
+               WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
+               WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+               WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+               WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+               WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+       }
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
         int r, i;
@@ -1080,6 +1142,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
         .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
         .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
+       .set_prt = gmc_v6_0_set_prt,
 };

 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
--
2.5.0

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