[PATCH RFC 2/2] drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM

[Michel Dänzer]

On 02/07/17 09:52 PM, Christian König wrote:
> Am 30.06.2017 um 17:18 schrieb John Brooks:
>> When a BO is moved to VRAM, clear AMDGPU_BO_FLAG_CPU_ACCESS. This
>> allows it
>> to potentially later move to invisible VRAM if the CPU does not access it
>> again.
>>
>> Setting the CPU_ACCESS flag in amdgpu_fault_reserve_notify() also means
>> that we can remove the loop to restrict lpfn to the end of visible VRAM,
>> because amdgpu_ttm_placement_init() will do it for us.
>>
>> Signed-off-by: John Brooks <john at fastquake.com>

[...]

>> @@ -446,6 +448,12 @@ static int amdgpu_move_ram_vram(struct
>> ttm_buffer_object *bo,
>>       if (unlikely(r)) {
>>           goto out_cleanup;
>>       }
>> +
>> +    /* The page fault handler will re-set this if the CPU accesses
>> the BO
>> +     * after it's moved.
>> +     */

Maybe say "amdgpu_bo_fault_reserve_notify" explicitly here instead of
"The page fault handler".


>> +    abo->flags &= ~AMDGPU_BO_FLAG_CPU_ACCESS;
>> +
> 
> This is the wrong place for clearing the flag. This code path is only
> called when we move things back in after suspend/resume (or run out of
> GTT space).

Surely amdgpu_move_ram_vram is called whenever a BO is moved to VRAM,
for any reason. I suggested clearing the flag here to John on IRC. The
idea is briefly described in the commit log, let me elaborate a bit on that:

When a BO is moved to VRAM which has the AMDGPU_BO_FLAG_CPU_ACCESS flag
set, it is put in CPU visible VRAM, and the flag is cleared. If the CPU
doesn't access the BO, the next time it will be moved to VRAM (after it
was evicted from there, for any reason), the flag will no longer be set,
and the BO will likely be moved to CPU invisible VRAM.

If the BO is accessed by the CPU again though (no matter where the BO is
currently located at that time), the flag is set again, and the cycle
from the previous paragraph starts over.

The end result should be similar as with the timestamp based solution in
John's earlier series: BOs which are at least occasionally accessed by
the CPU will tend to be in CPU visible VRAM, those which are never
accessed by the CPU can be in CPU invisible VRAM.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer