[PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Shaoyun Liu
> Sent: Tuesday, July 04, 2017 2:33 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
> 
> nbio hdp flush routine are called within atomic context.
> Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL
> register
> since this register has its own VF copy
> 
> Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6
> Signed-off-by: Shaoyun Liu <Shaoyun.Liu at amd.com>

Please split this patch in two, one to add the new macro, the next to convert the nbio code.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c    | 2 +-
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c    | 2 +-
>  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 7 +++++++
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 1e272f7..61c0028 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct
> amdgpu_device *adev, bool enable)
> 
>  void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
>  {
> -	WREG32_SOC15(NBIO, 0,
> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> +	WREG32_SOC15_NO_KIQ(NBIO, 0,
> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>  }
> 
>  u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index aa04632..11b70d6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct
> amdgpu_device *adev, bool enable)
> 
>  void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
>  {
> -	WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL,
> 0);
> +	WREG32_SOC15_NO_KIQ(NBIO, 0,
> mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>  }
> 
>  u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index e2d330e..7a8e4e28 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
>  		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
> reg : \
>  		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> 
> +#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> +	WREG32_NO_KIQ( (0 == reg##_BASE_IDX ?
> ip##_BASE__INST##inst##_SEG0 + reg : \
> +		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
> reg : \
> +		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 +
> reg : \
> +		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
> reg : \
> +		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> +
>  #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
>  	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0
> + reg : \
>  		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
> reg : \
> --
> 1.9.1
> 
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