[PATCH 49/81] drm/amd/display: dal1.1 hwseq prog update

[sunpeng.li at amd.com]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>

Change-Id: I201b96af4efc95077d3cc54c6fbe810b337cf4a1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 223bb79..4c39bf0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -64,17 +64,13 @@ static void enable_dppclk(
 			plane_id,
 			dppclk_div);
 
-	if (dppclk_div) {
-		/* 1/2 DISPCLK*/
+	if (hws->shifts->DPPCLK_RATE_CONTROL)
 		REG_UPDATE_2(DPP_CONTROL[plane_id],
-			DPPCLK_RATE_CONTROL, 1,
+			DPPCLK_RATE_CONTROL, dppclk_div,
 			DPP_CLOCK_ENABLE, 1);
-	} else {
-		/* DISPCLK */
-		REG_UPDATE_2(DPP_CONTROL[plane_id],
-			DPPCLK_RATE_CONTROL, 0,
+	else
+		REG_UPDATE(DPP_CONTROL[plane_id],
 			DPP_CLOCK_ENABLE, 1);
-	}
 }
 
 static void enable_power_gating_plane(
-- 
2.7.4