[PATCH 2/2] drm/amdgpu: Support IOMMU on Raven

[Christian König]

Am 27.07.2017 um 21:48 schrieb Yong Zhao:
> We achieved that by setting S(SYSTEM) and P(PDE as PTE) bit to 1 for
> PDEs and setting S bit to 1 for PTEs when the corresponding addresses
> are not occupied by gpu driver allocated buffers.
>
> Change-Id: I52e41b6e93243dbbd08d97781da1c9a60ce1f9a4
> Signed-off-by: Yong Zhao <Yong.Zhao at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 29 ++++++++++++++++++++++++-----
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  3 +++
>   2 files changed, 27 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 9325f39..d152724 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -288,6 +288,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>   	unsigned pt_idx, from, to;
>   	int r;
>   	u64 flags;
> +	uint64_t init_value = 0;
>   
>   	if (!parent->entries) {
>   		unsigned num_entries = amdgpu_vm_num_entries(adev, level);
> @@ -320,6 +321,12 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>   		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
>   				AMDGPU_GEM_CREATE_SHADOW);
>   
> +	if (vm->pte_support_ats) {
> +		init_value = AMDGPU_PTE_SYSTEM;
> +		if (level != adev->vm_manager.num_level - 1)
> +			init_value |= AMDGPU_PDE_PTE;
> +	}
> +
>   	/* walk over the address space and allocate the page tables */
>   	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
>   		struct reservation_object *resv = vm->root.bo->tbo.resv;
> @@ -332,7 +339,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>   					     AMDGPU_GPU_PAGE_SIZE, true,
>   					     AMDGPU_GEM_DOMAIN_VRAM,
>   					     flags,
> -					     NULL, resv, 0, &pt);
> +					     NULL, resv, init_value, &pt);
>   			if (r)
>   				return r;
>   
> @@ -1994,15 +2001,19 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
>   	struct amdgpu_bo_va_mapping *mapping;
>   	struct dma_fence *f = NULL;
>   	int r;
> +	uint64_t init_pte_value = 0;
>   
>   	while (!list_empty(&vm->freed)) {
>   		mapping = list_first_entry(&vm->freed,
>   			struct amdgpu_bo_va_mapping, list);
>   		list_del(&mapping->list);
>   
> +		if (vm->pte_support_ats)
> +			init_pte_value = AMDGPU_PTE_SYSTEM;
> +
>   		r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm,
>   						mapping->start, mapping->last,
> -						0, 0, &f);
> +						init_pte_value, 0, &f);
>   		amdgpu_vm_free_mapping(adev, vm, mapping, f);
>   		if (r) {
>   			dma_fence_put(f);
> @@ -2493,6 +2504,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   	struct amd_sched_rq *rq;
>   	int r, i;
>   	u64 flags;
> +	uint64_t init_pde_value = 0;
>   
>   	vm->va = RB_ROOT;
>   	vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
> @@ -2514,10 +2526,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   	if (r)
>   		return r;
>   
> -	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
> +	vm->pte_support_ats = false;
> +
> +	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
>   		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
>   						AMDGPU_VM_USE_CPU_FOR_COMPUTE);
> -	else
> +
> +		if (adev->asic_type == CHIP_RAVEN) {
> +			vm->pte_support_ats = true;
> +			init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE;
> +		}
> +	} else
>   		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
>   						AMDGPU_VM_USE_CPU_FOR_GFX);
>   	DRM_DEBUG_DRIVER("VM update mode is %s\n",
> @@ -2537,7 +2556,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   	r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
>   			     AMDGPU_GEM_DOMAIN_VRAM,
>   			     flags,
> -			     NULL, NULL, 0, &vm->root.bo);
> +			     NULL, NULL, init_pde_value, &vm->root.bo);
>   	if (r)
>   		goto error_free_sched_entity;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 34d9174..217ecba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -146,6 +146,9 @@ struct amdgpu_vm {
>   
>   	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
>   	bool                    use_cpu_for_update;
> +
> +	/* Flag to indicate ATS support from PTE for GFX9 */
> +	bool			pte_support_ats;
>   };
>   
>   struct amdgpu_vm_id {