[PATCH 3/3] drm/amdgpu: fix Vega10 HW config for 2MB pages

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Saturday, July 29, 2017 7:32 AM
> To: amd-gfx at lists.freedesktop.org
> Subject: [PATCH 3/3] drm/amdgpu: fix Vega10 HW config for 2MB pages
> 
> From: Christian König <christian.koenig at amd.com>
> 
> Those values weren't correct. This should result in quite some speedup.
> 
> Signed-off-by: Christian König <christian.koenig at amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 408723e..6c8040e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -144,8 +144,8 @@ static void gfxhub_v1_0_init_cache_regs(struct
> amdgpu_device *adev)
>  	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
> 
>  	tmp = mmVM_L2_CNTL3_DEFAULT;
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
> L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
> +	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
> +	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
> L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
>  	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
> 
>  	tmp = mmVM_L2_CNTL4_DEFAULT;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index ad8def3..74cb647 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -158,8 +158,8 @@ static void mmhub_v1_0_init_cache_regs(struct
> amdgpu_device *adev)
>  	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
> 
>  	tmp = mmVM_L2_CNTL3_DEFAULT;
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
> L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
> +	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
> +	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
> L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
>  	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
> 
>  	tmp = mmVM_L2_CNTL4_DEFAULT;
> --
> 2.7.4
> 
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