[PATCH] drm/amdgpu: fix solid screen and hard hang when 2k + 4k display connected with DP

[Christian König]

Am 26.06.2017 um 12:53 schrieb Huang Rui:
> On Mon, Jun 26, 2017 at 03:18:52PM +0800, Christian König wrote:
>> Am 26.06.2017 um 09:03 schrieb Huang Rui:
>>> Signed-off-by: Huang Rui <ray.huang at amd.com>
>>> Cc: Xiaojie Yuan <Xiaojie.Yuan at amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/
>> amdgpu/amdgpu_psp.c
>>> index 5bed483..60d0455 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> @@ -130,7 +130,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
>>>         ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
>>>                              fence_mc_addr, index);
>>>   
>>> -     while (*((unsigned int *)psp->fence_buf) != index) {
>>> +     while (*((unsigned int *)psp->fence_buf) < index) {
>> That is still horrible incorrect. At bare minimum you need to use the
>> READ_ONCE() macro here.
>>
> So, READ_ONCE(*((unsigned int *)psp->fence_buf)) < index.
> Do you mean the complier might cause to read the previous fence buffer
> value if we don't add READ_ONCE?

Yes, exactly. I would guess that this only works by coincident because 
the msleep() is causing a barrier here.

Christian.

>
>> But it would be even better to completely drop this and use the fence
>> implementation in amdgpu_fence.c as well.
>>
> I understand, I will refactor it after S3 stress completed.
>
> Thanks,
> Ray