[PATCH] drm/amdgpu: Changed CU reservation golden settings

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of ozeng
> Sent: Tuesday, June 27, 2017 4:11 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zeng, Oak
> Subject: [PATCH] drm/amdgpu: Changed CU reservation golden settings
> 
> With previous golden settings, compute task can't use
> reserved LDS (32K) on CU0 and CU1. On 64K LDS system,
> if compute work group allocate more than 32K LDS, then
> it can't be dispatched to CU0 and CU1 because of the
> reservation. This enables compute task to use reserved
> LDS on CU0 and CU1.
> 
> Signed-off-by: Oak Zeng <Oak.Zeng at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 28 ++++++++++++++------------
> --
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 547db32..3b886a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -193,8 +193,8 @@ static const u32 tonga_golden_common_all[] =
>  	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
>  	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
>  	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
> +	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
>  };
> 
>  static const u32 tonga_mgcg_cgcg_init[] =
> @@ -303,8 +303,8 @@ static const u32 polaris11_golden_common_all[] =
>  	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
>  	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
>  	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
>  };
> 
>  static const u32 golden_settings_polaris10_a11[] =
> @@ -336,8 +336,8 @@ static const u32 polaris10_golden_common_all[] =
>  	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
>  	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
>  	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
>  };
> 
>  static const u32 fiji_golden_common_all[] =
> @@ -348,8 +348,8 @@ static const u32 fiji_golden_common_all[] =
>  	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
>  	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
>  	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
>  	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
>  	mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
>  };
> @@ -436,8 +436,8 @@ static const u32 iceland_golden_common_all[] =
>  	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
>  	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
>  	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
> +	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
>  };
> 
>  static const u32 iceland_mgcg_cgcg_init[] =
> @@ -532,8 +532,8 @@ static const u32 cz_golden_common_all[] =
>  	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
>  	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
>  	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
> +	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
>  };
> 
>  static const u32 cz_mgcg_cgcg_init[] =
> @@ -637,8 +637,8 @@ static const u32 stoney_golden_common_all[] =
>  	mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
>  	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
>  	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
> -	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
> +	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
>  };
> 
>  static const u32 stoney_mgcg_cgcg_init[] =
> --
> 2.7.4
> 
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