[PATCH 0/1] Add infrastructure for handling underlay planes

[Shirish S]

I would like to use this letter to explain what this patche does.
(Note its tested on Carrizo & Stoney)

* Firstly it decouples the per-plane per-crtc design, as a result,
  now with the unit test called as 'modetest' we can see 3 planes
  and 2 crtc's compared to what it was 2 planes for 2 crtc's w/o
  this patch.
* I have introduced new variable of max_surfaces to the public
  caps structure that can be used for all asic's in future as well.
  Basic understanding being:
	max_streams 	== crtc
	link_count 	== connector 
	max_surfaces 	== plane
* The drm device initialization loops now for number of surfaces
  instead of stream.
* Have taken care that it won't break other asic's 
* Am able to reach __setplane_internal() in drm_plane.c which
  does the final update to plane, had to put a sanity patch there
  as we do not have update_plane() and disable_plane() implemented
   --> also testifies, that now we are able to handle planes with
  this patch.
* The YUV formats supported right now are default, will refine it
  going further.


Shirish S (1):
  drm/amd/display: decouple per-crtc-plane model

 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h           |  8 +++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 67 ++++++++++++++-----
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 77 +++++++++++++++-------
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h    |  5 +-
 drivers/gpu/drm/amd/display/dc/dc.h                |  1 +
 .../drm/amd/display/dc/dce100/dce100_resource.c    |  2 +
 .../drm/amd/display/dc/dce110/dce110_resource.c    |  2 +
 .../drm/amd/display/dc/dce112/dce112_resource.c    |  2 +
 .../drm/amd/display/dc/dce120/dce120_resource.c    |  2 +
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |  2 +
 10 files changed, 127 insertions(+), 41 deletions(-)

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2.7.4