[PATCH 0/1] Add infrastructure for handling underlay planes

[Shirish S]

On Fri, Mar 17, 2017 at 1:37 PM, Michel Dänzer <michel at daenzer.net> wrote:
>
> On 17/03/17 04:51 PM, Shirish S wrote:
> > I would like to use this letter to explain what this patche does.
> > (Note its tested on Carrizo & Stoney)
> >
> > * Firstly it decouples the per-plane per-crtc design, as a result,
> >   now with the unit test called as 'modetest' we can see 3 planes
> >   and 2 crtc's compared to what it was 2 planes for 2 crtc's w/o
> >   this patch.
> > * I have introduced new variable of max_surfaces to the public
> >   caps structure that can be used for all asic's in future as well.
> >   Basic understanding being:
> >       max_streams     == crtc
> >       link_count      == connector
> >       max_surfaces    == plane
> > * The drm device initialization loops now for number of surfaces
> >   instead of stream.
> > * Have taken care that it won't break other asic's
> > * Am able to reach __setplane_internal() in drm_plane.c which
> >   does the final update to plane, had to put a sanity patch there
> >   as we do not have update_plane() and disable_plane() implemented
> >    --> also testifies, that now we are able to handle planes with
> >   this patch.
> > * The YUV formats supported right now are default, will refine it
> >   going further.
>
> Sounds nice.
>
> BTW, are you aware of the KMS tests in the intel-gpu-tools tree
> (https://cgit.freedesktop.org/xorg/app/intel-gpu-tools/)? There should
> be much more comprehensive tests for this functionality there compared
> to modetest.
Yes, there are several auto tests as well i would like to be tested, but
there are more patches to follow, as this is just the basic
infrastructure to plumb
hardware capabilities to user space via drm-framework,
plumbing back to hardware is WIP.
>
>
> --
> Earthling Michel Dänzer               |               http://www.amd.com
> Libre software enthusiast             |             Mesa and X developer