[PATCH umr] sync up registers/bits with staging tree

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
---
 scripts/parse_bits.sh    | 4 +++-
 src/lib/ip/dce60_bits.i  | 1 +
 src/lib/ip/smu712_regs.i | 1 +
 src/lib/ip/smu713_regs.i | 1 +
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/scripts/parse_bits.sh b/scripts/parse_bits.sh
index ebaa6aefb1fa..14df5e831b01 100755
--- a/scripts/parse_bits.sh
+++ b/scripts/parse_bits.sh
@@ -4,7 +4,9 @@
 # ASICs
 
 #this is the path to the tree (not necessarily the one running on your host)
-pk=/nas/work/repos/linux/drivers/gpu/drm/amd/include/asic_reg/
+if [ "$pk" == "" ]; then
+	pk=/nas/work/repos/linux/drivers/gpu/drm/amd/include/asic_reg/
+fi
 
 # parse_bits /path/to/asic_reg/foo/block /path/to/umr/file
 parse_bits() {
diff --git a/src/lib/ip/dce60_bits.i b/src/lib/ip/dce60_bits.i
index 50ae01e400d5..7ced97afed5d 100644
--- a/src/lib/ip/dce60_bits.i
+++ b/src/lib/ip/dce60_bits.i
@@ -2488,6 +2488,7 @@ static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
 };
 static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
 	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZALIA_ENDPOINT_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
 };
 static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
 	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
diff --git a/src/lib/ip/smu712_regs.i b/src/lib/ip/smu712_regs.i
index eb030979eaec..f718b000b84b 100644
--- a/src/lib/ip/smu712_regs.i
+++ b/src/lib/ip/smu712_regs.i
@@ -1222,6 +1222,7 @@
 	{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, &ixCG_THERMAL_INT_ENA[0], sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
 	{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, &ixCG_THERMAL_INT_CTRL[0], sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
 	{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, &ixCG_THERMAL_INT_STATUS[0], sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixCURRENT_PG_STATUS_APU", REG_SMC, 0xd020029c, NULL, 0, 0, 0 },
 	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
 	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
 	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
diff --git a/src/lib/ip/smu713_regs.i b/src/lib/ip/smu713_regs.i
index 0f1d79aa2b9f..8a632b41624e 100644
--- a/src/lib/ip/smu713_regs.i
+++ b/src/lib/ip/smu713_regs.i
@@ -1192,6 +1192,7 @@
 	{ "ixGC_CAC_ACC_CU13", REG_SMC, 0xc7, &ixGC_CAC_ACC_CU13[0], sizeof(ixGC_CAC_ACC_CU13)/sizeof(ixGC_CAC_ACC_CU13[0]), 0, 0 },
 	{ "ixGC_CAC_ACC_CU14", REG_SMC, 0xc8, &ixGC_CAC_ACC_CU14[0], sizeof(ixGC_CAC_ACC_CU14)/sizeof(ixGC_CAC_ACC_CU14[0]), 0, 0 },
 	{ "ixGC_CAC_ACC_CU15", REG_SMC, 0xc9, &ixGC_CAC_ACC_CU15[0], sizeof(ixGC_CAC_ACC_CU15)/sizeof(ixGC_CAC_ACC_CU15[0]), 0, 0 },
+	{ "ixCURRENT_PG_STATUS_APU", REG_SMC, 0xd020029c, NULL, 0, 0, 0 },
 	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
 	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
 	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
-- 
2.12.0