[PATCH libdrm 7/7] tests/amdgpu: add Polaris12 support for cs test

[Marek Olšák]

From: Junwei Zhang <Jerry.Zhang at amd.com>

Signed-off-by: Junwei Zhang <Jerry.Zhang at amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang at amd.com>
---
 tests/amdgpu/cs_tests.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 0885d97..342815d 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -209,21 +209,22 @@ static void amdgpu_cs_uvd_create(void)
 
 	r = amdgpu_bo_cpu_map(buf_handle, &msg);
 	CU_ASSERT_EQUAL(r, 0);
 
 	memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		((uint8_t*)msg)[0x10] = 7;
 		/* chip beyond polaris 10/11 */
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64)) {
 			/* dpb size */
 			((uint8_t*)msg)[0x28] = 0x00;
 			((uint8_t*)msg)[0x29] = 0x94;
 			((uint8_t*)msg)[0x2A] = 0x6B;
 			((uint8_t*)msg)[0x2B] = 0x00;
 		}
 	}
 
 	r = amdgpu_bo_cpu_unmap(buf_handle);
 	CU_ASSERT_EQUAL(r, 0);
@@ -289,21 +290,22 @@ static void amdgpu_cs_uvd_decode(void)
 	CU_ASSERT_EQUAL(r, 0);
 
 	memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		ptr[0x10] = 7;
 		ptr[0x98] = 0x00;
 		ptr[0x99] = 0x02;
 		/* chip beyond polaris10/11 */
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64)) {
 			/* dpb size */
 			ptr[0x24] = 0x00;
 			ptr[0x25] = 0x94;
 			ptr[0x26] = 0x6B;
 			ptr[0x27] = 0x00;
 			/*ctx size */
 			ptr[0x2C] = 0x00;
 			ptr[0x2D] = 0xAF;
 			ptr[0x2E] = 0x50;
 			ptr[0x2F] = 0x00;
@@ -334,38 +336,40 @@ static void amdgpu_cs_uvd_decode(void)
 	fb_addr = msg_addr + 4*1024;
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		it_addr = fb_addr + 4*1024;
 		bs_addr = it_addr + 4*1024;
 	} else
 		bs_addr = fb_addr + 4*1024;
 	dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64)) {
 			ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 		}
 	}
 
 	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 
 	i = 0;
 	uvd_cmd(msg_addr, 0x0, &i);
 	uvd_cmd(dpb_addr, 0x1, &i);
 	uvd_cmd(dt_addr, 0x2, &i);
 	uvd_cmd(fb_addr, 0x3, &i);
 	uvd_cmd(bs_addr, 0x100, &i);
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		uvd_cmd(it_addr, 0x204, &i);
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A))
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64))
 			uvd_cmd(ctx_addr, 0x206, &i);
 	}
 
 	ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
 	ib_cpu[i++] = 0x1;
 	for (; i % 16; ++i)
 		ib_cpu[i] = 0x80000000;
 
 	r = submit(i, AMDGPU_HW_IP_UVD);
 	CU_ASSERT_EQUAL(r, 0);
-- 
2.7.4