[PATCH 3/3] drm/amdgpu/soc15: return cached values for some registers

Christian K├Ânig deathsimple at vodafone.de
Fri Mar 24 19:44:59 UTC 2017


Am 24.03.2017 um 20:13 schrieb Alex Deucher:
> Required for SR-IOV and saves MMIO transactions.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

As far as I can see they are not used any more by userspace and the same 
info is available in enabled_rb_pipes_mask.

So why do you want to keep them?

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/soc15.c | 40 ++++++++++++++++++++++++++++++--------
>   1 file changed, 32 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 804bd8d..441e0f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -322,6 +322,32 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
>   	return val;
>   }
>   
> +static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
> +					 bool indexed, u32 se_num,
> +					 u32 sh_num, u32 reg_offset)
> +{
> +	if (indexed) {
> +		unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
> +		unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
> +
> +		switch (reg_offset) {
> +		case SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE):
> +			return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
> +		case SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE):
> +			return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
> +		}
> +
> +		return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
> +	} else {
> +		switch (reg_offset) {
> +		case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
> +			return adev->gfx.config.gb_addr_config;
> +		default:
> +			return RREG32(reg_offset);
> +		}
> +	}
> +}
> +
>   static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
>   			    u32 sh_num, u32 reg_offset, u32 *value)
>   {
> @@ -345,10 +371,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
>   			if (reg_offset != asic_register_entry->reg_offset)
>   				continue;
>   			if (!asic_register_entry->untouched)
> -				*value = asic_register_entry->grbm_indexed ?
> -					soc15_read_indexed_register(adev, se_num,
> -								 sh_num, reg_offset) :
> -					RREG32(reg_offset);
> +				*value = soc15_get_register_value(adev,
> +								  asic_register_entry->grbm_indexed,
> +								  se_num, sh_num, reg_offset);
>   			return 0;
>   		}
>   	}
> @@ -358,10 +383,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
>   			continue;
>   
>   		if (!soc15_allowed_read_registers[i].untouched)
> -			*value = soc15_allowed_read_registers[i].grbm_indexed ?
> -				soc15_read_indexed_register(adev, se_num,
> -							 sh_num, reg_offset) :
> -				RREG32(reg_offset);
> +			*value = soc15_get_register_value(adev,
> +							  soc15_allowed_read_registers[i].grbm_indexed,
> +							  se_num, sh_num, reg_offset);
>   		return 0;
>   	}
>   	return -EINVAL;




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