[PATCH libdrm] amdgpu: stop reading CC_RB_BACKEND_DISABLE on Vega10

Marek Olšák maraeo at gmail.com
Mon Mar 27 13:48:37 UTC 2017


Reviewed-by: Marek Olšák <marek.olsak at amd.com>

Marek

On Mon, Mar 27, 2017 at 3:44 PM, Christian König
<deathsimple at vodafone.de> wrote:
> From: Christian König <christian.koenig at amd.com>
>
> Follow up to 'drm: don't access deprecated register on Vega10'.
>
> The same information is available in enabled_rb_pipes_mask and reading that
> register can cause GRBM bus problems.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
> ---
>  amdgpu/amdgpu_gpu_info.c | 24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
> index 14754fb..1b39c96 100644
> --- a/amdgpu/amdgpu_gpu_info.c
> +++ b/amdgpu/amdgpu_gpu_info.c
> @@ -176,20 +176,20 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
>         dev->info.vce_harvest_config = dev->dev_info.vce_harvest_config;
>         dev->info.pci_rev_id = dev->dev_info.pci_rev;
>
> -       for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
> -               unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
> -                                   (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
> -                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
> +       if (dev->info.family_id < AMDGPU_FAMILY_AI) {
> +               for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
> +                       unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
> +                                           (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
> +                                            AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
>
> -               r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
> -                                            &dev->info.backend_disable[i]);
> -               if (r)
> -                       return r;
> -               /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
> -               dev->info.backend_disable[i] =
> -                       (dev->info.backend_disable[i] >> 16) & 0xff;
> +                       r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
> +                                                    &dev->info.backend_disable[i]);
> +                       if (r)
> +                               return r;
> +                       /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
> +                       dev->info.backend_disable[i] =
> +                               (dev->info.backend_disable[i] >> 16) & 0xff;
>
> -               if (dev->info.family_id < AMDGPU_FAMILY_AI) {
>                         r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
>                                                      &dev->info.pa_sc_raster_cfg[i]);
>                         if (r)
> --
> 2.5.0
>
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