[PATCH] drm/amdgpu: fix DRM clockgating incorrect reading

[Deucher, Alexander]

> -----Original Message-----
> From: Huang Rui [mailto:ray.huang at amd.com]
> Sent: Monday, March 27, 2017 2:50 AM
> To: amd-gfx at lists.freedesktop.org; Deucher, Alexander
> Cc: Quan, Evan; Huang, Ray
> Subject: [PATCH] drm/amdgpu: fix DRM clockgating incorrect reading
> 
> Reported-by: Evan Quan <evan.quan at amd.com>
> Reported-by: Xiangliang Yu <Xiangliang.Yu at amd.com>
> Signed-off-by: Huang Rui <ray.huang at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 8f460f6..fba9675 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -815,13 +815,13 @@ static void
> soc15_common_get_clockgating_state(void *handle, u32 *flags)
>  		*flags |= AMD_CG_SUPPORT_HDP_LS;
> 
>  	/* AMD_CG_SUPPORT_DRM_MGCG */
> -	data = RREG32(SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_CGTT_DRM_CLK_CTRL0));
> -	if (!(data &
> MP0_SMN_CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
> +	data = RREG32(SOC15_REG_OFFSET(MP0, 0,
> mmMP0_MISC_CGTT_CTRL0));
> +	if (!(data & 0x01000000))
>  		*flags |= AMD_CG_SUPPORT_DRM_MGCG;
> 
>  	/* AMD_CG_SUPPORT_DRM_LS */
> -	data = RREG32(SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_DRM_LIGHT_SLEEP_CTRL));
> -	if (data &
> MP0_SMN_DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK)
> +	data = RREG32(SOC15_REG_OFFSET(MP0, 0,
> mmMP0_MISC_LIGHT_SLEEP_CTRL));
> +	if (data & 0x1)
>  		*flags |= AMD_CG_SUPPORT_DRM_LS;
> 
>  	/* AMD_CG_SUPPORT_ROM_MGCG */
> --
> 2.7.4