[PATCH] drm/amd/powerplay: implemnent force dpm level on Vega10.

[Rex Zhu]

Change-Id: I13daa4ab9bdbd5a850e3ecf784fae43b19a126c9
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 38 ++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 43e5d777..235c8a3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3393,16 +3393,31 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
 
 	if (!data->registry_data.sclk_dpm_key_disabled) {
 		if (data->smc_state_table.gfx_boot_level !=
-				data->dpm_table.gfx_table.dpm_state.soft_min_level)
+				data->dpm_table.gfx_table.dpm_state.soft_min_level) {
+				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
+				hwmgr->smumgr,
+				PPSMC_MSG_SetSoftMinGfxclkByIndex,
+				data->smc_state_table.gfx_boot_level),
+				"Failed to set soft min sclk index!",
+				return -EINVAL);
 			data->dpm_table.gfx_table.dpm_state.soft_min_level =
 					data->smc_state_table.gfx_boot_level;
+		}
 	}
 
 	if (!data->registry_data.mclk_dpm_key_disabled) {
 		if (data->smc_state_table.mem_boot_level !=
-				data->dpm_table.mem_table.dpm_state.soft_min_level)
+				data->dpm_table.mem_table.dpm_state.soft_min_level) {
+				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
+				hwmgr->smumgr,
+				 PPSMC_MSG_SetSoftMinUclkByIndex,
+				data->smc_state_table.mem_boot_level),
+				"Failed to set soft min mclk index!",
+				return -EINVAL);
+
 			data->dpm_table.mem_table.dpm_state.soft_min_level =
 					data->smc_state_table.mem_boot_level;
+		}
 	}
 
 	return 0;
@@ -3418,6 +3433,12 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
 	if (!data->registry_data.sclk_dpm_key_disabled) {
 		if (data->smc_state_table.gfx_max_level !=
 				data->dpm_table.gfx_table.dpm_state.soft_max_level) {
+				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
+				hwmgr->smumgr,
+				PPSMC_MSG_SetSoftMaxGfxclkByIndex,
+				data->smc_state_table.gfx_max_level),
+				"Failed to set soft max sclk index!",
+				return -EINVAL);
 			data->dpm_table.gfx_table.dpm_state.soft_max_level =
 					data->smc_state_table.gfx_max_level;
 		}
@@ -3426,6 +3447,12 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
 	if (!data->registry_data.mclk_dpm_key_disabled) {
 		if (data->smc_state_table.mem_max_level !=
 				data->dpm_table.mem_table.dpm_state.soft_max_level) {
+				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
+				hwmgr->smumgr,
+				PPSMC_MSG_SetSoftMaxUclkByIndex,
+				data->smc_state_table.mem_max_level),
+				"Failed to set soft max mclk index!",
+				return -EINVAL);
 			data->dpm_table.mem_table.dpm_state.soft_max_level =
 					data->smc_state_table.mem_max_level;
 		}
@@ -3443,6 +3470,7 @@ static int vega10_generate_dpm_level_enable_mask(
 			(const struct phm_set_power_state_input *)input;
 	const struct vega10_power_state *vega10_ps =
 			cast_const_phw_vega10_power_state(states->pnew_state);
+	int i;
 
 	PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
 			"Attempt to Trim DPM States Failed!",
@@ -3463,6 +3491,12 @@ static int vega10_generate_dpm_level_enable_mask(
 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
 			"Attempt to upload DPM Max Levels Failed!",
 			return -1);
+	for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
+		data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
+
+
+	for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
+		data->dpm_table.mem_table.dpm_levels[i].enabled = true;
 
 	return 0;
 }
-- 
1.9.1