[PATCH 12/15] drm/amdgpu: limit block size to one page

[Zhang, Jerry (Junwei)]

On 03/27/2017 01:53 PM, Chunming Zhou wrote:
> Change-Id: I00ff5d2c7ff29563394cb8af4c57780b91876743
> Signed-off-by: Chunming Zhou <David1.Zhou at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7bad6b6..4041d72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1079,6 +1079,14 @@ static bool amdgpu_check_pot_argument(int arg)
>
>   static void amdgpu_get_block_size(struct amdgpu_device *adev)
>   {
> +	/* from AI, asic starts to support multiple level VMPT */
> +	if (adev->family >= AMDGPU_FAMILY_AI) {
> +		if (amdgpu_vm_block_size != 9)
> +			dev_warn(adev->dev, "Multi-VMPT limits block size to"
> +				 "one page!\n");
> +		amdgpu_vm_block_size = 9;

Do you mean for multi-VMPT, the block size must be 9?
Is that related to page level?

Jerry

> +		return;
> +	}
>   	/* defines number of bits in page table versus page directory,
>   	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
>   	 * page table and the remaining bits are in the page directory */
>