[PATCH 12/12] drm/amd/display: obtain usHBR3En bit from BP 1

Harry Wentland harry.wentland at amd.com
Tue Mar 28 21:09:55 UTC 2017


From: Ding Wang <Ding.Wang at amd.com>

ASICs using bios parser 1 don't check HBR3 capability as there is no such
a bit usHBR3En in ATOM_ENCODER_CAP_RECORDER.
Therefore, will use ATOM_ENCODER_CAP_RECORDER_V2 and thus obtain the usHBR3En
bit.

Change-Id: I05e3fa6bfcbe9e55cb3ea2ff736dfc3c0b1b8a9f
Signed-off-by: Ding Wang <ding.wang at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c     | 14 +++++++-------
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 50163a06a653..47a467688073 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -88,7 +88,7 @@ static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
 static struct device_id device_type_from_device_id(uint16_t device_id);
 static uint32_t signal_to_ss_id(enum as_signal_type signal);
 static uint32_t get_support_mask_for_device_id(struct device_id device_id);
-static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
+static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(
 	struct bios_parser *bp,
 	ATOM_OBJECT *object);
 
@@ -1837,7 +1837,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	ATOM_OBJECT *object;
-	ATOM_ENCODER_CAP_RECORD *record = NULL;
+	ATOM_ENCODER_CAP_RECORD_V2 *record = NULL;
 
 	if (!info)
 		return BP_RESULT_BADINPUT;
@@ -1851,8 +1851,8 @@ static enum bp_result bios_parser_get_encoder_cap_info(
 	if (!record)
 		return BP_RESULT_NORECORD;
 
-	info->DP_HBR2_CAP = record->usHBR2Cap;
 	info->DP_HBR2_EN = record->usHBR2En;
+	info->DP_HBR3_EN = record->usHBR3En;
 	return BP_RESULT_OK;
 }
 
@@ -1867,9 +1867,9 @@ static enum bp_result bios_parser_get_encoder_cap_info(
  * @return atom encoder cap record
  *
  * @note
- *  search all records to find the ATOM_ENCODER_CAP_RECORD record
+ *  search all records to find the ATOM_ENCODER_CAP_RECORD_V2 record
  */
-static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
+static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(
 	struct bios_parser *bp,
 	ATOM_OBJECT *object)
 {
@@ -1899,8 +1899,8 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
 		if (ATOM_ENCODER_CAP_RECORD_TYPE != header->ucRecordType)
 			continue;
 
-		if (sizeof(ATOM_ENCODER_CAP_RECORD) <= header->ucRecordSize)
-			return (ATOM_ENCODER_CAP_RECORD *)header;
+		if (sizeof(ATOM_ENCODER_CAP_RECORD_V2) <= header->ucRecordSize)
+			return (ATOM_ENCODER_CAP_RECORD_V2 *)header;
 	}
 
 	return NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index df116f86ab45..1a84ee0105da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -993,7 +993,7 @@ bool dce110_link_encoder_construct(
 			enc110->base.ctx->dc_bios, enc110->base.id,
 			&bp_cap_info)) {
 		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
-				bp_cap_info.DP_HBR2_CAP;
+				bp_cap_info.DP_HBR2_EN;
 		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 				bp_cap_info.DP_HBR3_EN;
 	}
-- 
2.11.0



More information about the amd-gfx mailing list