[PATCH 1/3] drm/amdgpu: Make max_pfn 64-bit

[Christian König]

Am 29.03.2017 um 03:00 schrieb Felix Kuehling:
> With 4-level page tables the maximum VM size is 256TB. That's 64G
> pages, which can't be represented in 32-bit.
>
> Signed-off-by: Felix Kuehling <Felix.Kuehling at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 4 ++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h   | 2 +-
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +++--
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 5 +++--
>   4 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index f4cb7de..818747f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -336,7 +336,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
>   			struct amdgpu_vm *vm,
>   			uint64_t saddr, uint64_t size)
>   {
> -	unsigned last_pfn;
> +	uint64_t last_pfn;
>   	uint64_t eaddr;
>   
>   	/* validate the parameters */
> @@ -346,7 +346,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
>   	eaddr = saddr + size - 1;
>   	last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
>   	if (last_pfn >= adev->vm_manager.max_pfn) {
> -		dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n",
> +		dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
>   			last_pfn, adev->vm_manager.max_pfn);
>   		return -EINVAL;
>   	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index b5e5cdd..102b1f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -153,7 +153,7 @@ struct amdgpu_vm_manager {
>   	u64					fence_context;
>   	unsigned				seqno[AMDGPU_MAX_RINGS];
>   
> -	uint32_t				max_pfn;
> +	uint64_t				max_pfn;
>   	uint32_t				num_level;
>   	/* vram base address for page table entry  */
>   	u64					vram_base_offset;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 5604a53..dd48637 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -227,8 +227,9 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
>   		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
>   		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
> -				adev->vm_manager.max_pfn - 1);
> -		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, 0);
> +			lower_32_bits(adev->vm_manager.max_pfn - 1));
> +		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
> +			upper_32_bits(adev->vm_manager.max_pfn - 1));
>   	}
>   
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 5903bb0..c1dc8c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -247,8 +247,9 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
>   		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
>   		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
> -				adev->vm_manager.max_pfn - 1);
> -		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, 0);
> +			lower_32_bits(adev->vm_manager.max_pfn - 1));
> +		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
> +			upper_32_bits(adev->vm_manager.max_pfn - 1));
>   	}
>   
>   	return 0;