[PATCH 2/6] drm/amdgpu: reset GDW, GWS and OA software copy to update them

Ding, Pixel Pixel.Ding at amd.com
Thu May 4 08:13:34 UTC 2017


In theory this patch is mandatory. It fixes the VM fault issue after TDR on Tonga. You can remove it when you rewrite TDR, but currently Tonga GPU reset has problem without this patch if MCBP is enabled. We need to flush GDS after reset, it’s bypassed if the SW state is not cleaned.

— 
Sincerely Yours,
Pixel







On 04/05/2017, 3:28 PM, "Liu, Monk" <Monk.Liu at amd.com> wrote:

>NAK, this patch is not needed currently
>
>1, Because TDR feature is still undergoing, so all patches related with TDR should pending now
>2, I don't think this is needed, @Pixel can you get the latest amd-staging-4.9 driver and try it, see if the "vm fault" duplicated without this patch?  Because I remember no such issue In staging driver 
>
>BR Monk
>
>-----Original Message-----
>From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of Xiangliang Yu
>Sent: Thursday, May 04, 2017 2:34 PM
>To: amd-gfx at lists.freedesktop.org
>Cc: Ding, Pixel <Pixel.Ding at amd.com>; Yu, Xiangliang <Xiangliang.Yu at amd.com>
>Subject: [PATCH 2/6] drm/amdgpu: reset GDW, GWS and OA software copy to update them
>
>From: Pixel Ding <Pixel.Ding at amd.com>
>
>Reset GDW, GWS and OA when SRIOV do reset.
>
>Signed-off-by: Pixel Ding <Pixel.Ding at amd.com>
>Signed-off-by: Xiangliang Yu <Xiangliang.Yu at amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index aef2019..f11241d 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -2538,7 +2538,7 @@ static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
>  */
> int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)  {
>-	int i, r = 0;
>+	int i, j, r = 0;
> 	int resched;
> 	struct amdgpu_bo *bo, *tmp;
> 	struct amdgpu_ring *ring;
>@@ -2616,6 +2616,14 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
> 	}
> 	fence_put(fence);
> 
>+	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
>+		struct amdgpu_vm_id_manager *id_mgr =
>+			&adev->vm_manager.id_mgr[i];
>+
>+		for (j = 1; j < id_mgr->num_ids; j++)
>+			amdgpu_vm_reset_id(adev, i, j);
>+	}
>+
> 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
> 		struct amdgpu_ring *ring = adev->rings[i];
> 		if (!ring || !ring->sched.thread)
>--
>2.7.4
>
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