[PATCH 6/6] drm/amdgpu: clean doorbell after sending init table to mmsch

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Xiangliang Yu
> Sent: Thursday, May 04, 2017 2:38 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Yu, Xiangliang; Min, Frank
> Subject: [PATCH 6/6] drm/amdgpu: clean doorbell after sending init table to
> mmsch
> 
> From: Frank Min <Frank.Min at amd.com>
> 
> According to HW design, need to clean doorbell after setup MMSCH
> table.
> 
> Signed-off-by: Frank Min <Frank.Min at amd.com>
> Signed-off-by: Xiangliang Yu <Xiangliang.Yu at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1 +
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 6e9359d..8af2921 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -696,6 +696,7 @@ static int uvd_v7_0_mmsch_start(struct
> amdgpu_device *adev,
>  		dev_err(adev->dev, "failed to init MMSCH,
> mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
>  		return -EBUSY;
>  	}
> +	WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);

Just double checking, does VCE only use 32 bit doorbells?  Gfx uses 64 bit doorbells.  With that confirmed:
Acked-by: Alex Deucher <alexander.deucher at amd.com>

> 
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 661f883..9f73cc1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -190,6 +190,7 @@ static int vce_v4_0_mmsch_start(struct
> amdgpu_device *adev,
>  		dev_err(adev->dev, "failed to init MMSCH,
> mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
>  		return -EBUSY;
>  	}
> +	WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
> 
>  	return 0;
>  }
> --
> 2.7.4
> 
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