[PATCH 1/2] drm/amdgpu: fix ring0 failed on firepro card

[Christian König]

We should really improve the order in which blocks are handled.

Having all this special order handling in amdgpu_device.c and for SRIOV 
is really not a good idea.

Anyway, patch is Acked-by: Christian König <christian.koenig at amd.com> 
for now.

Regards,
Christian.

Am 05.05.2017 um 09:46 schrieb He, Hongbo:
> Looks fine to me, Reviewed-by: Roger.He <Hongbo.He at amd.com>
>
> BTW,  I have noticed  SRIOV has more IP resume in first phase, maybe also needed for bare metal for other ASIC.
>
> Thanks
> Roger(Hongbo.He)
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of Chunming Zhou
> Sent: Friday, May 05, 2017 2:46 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhou, David(ChunMing)
> Subject: [PATCH 1/2] drm/amdgpu: fix ring0 failed on firepro card
>
> the root cause is vram content is lost completely after pci reset.
>
> Change-Id: I012cea984702894410b0f05149fd017bb62b624c
> Signed-off-by: Chunming Zhou <David1.Zhou at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 57 ++++++++++++++++++++++++++----
>   1 file changed, 50 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 8a75327..b44ecdb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1787,13 +1787,40 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> -static int amdgpu_resume(struct amdgpu_device *adev)
> +static int amdgpu_resume_phase1(struct amdgpu_device *adev)
>   {
>   	int i, r;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
>   		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> +		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
> +				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
> +				adev->ip_blocks[i].version->type ==
> +				AMD_IP_BLOCK_TYPE_IH) {
> +			r = adev->ip_blocks[i].version->funcs->resume(adev);
> +			if (r) {
> +				DRM_ERROR("resume of IP block <%s> failed %d\n",
> +					  adev->ip_blocks[i].version->funcs->name, r);
> +				return r;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int amdgpu_resume_phase2(struct amdgpu_device *adev) {
> +	int i, r;
> +
> +	for (i = 0; i < adev->num_ip_blocks; i++) {
> +		if (!adev->ip_blocks[i].status.valid)
> +			continue;
> +		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
> +				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
> +				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
> +			continue;
>   		r = adev->ip_blocks[i].version->funcs->resume(adev);
>   		if (r) {
>   			DRM_ERROR("resume of IP block <%s> failed %d\n", @@ -1805,6 +1832,18 @@ static int amdgpu_resume(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> +static int amdgpu_resume(struct amdgpu_device *adev) {
> +	int r;
> +
> +	r = amdgpu_resume_phase1(adev);
> +	if (r)
> +		return r;
> +	r = amdgpu_resume_phase2(adev);
> +
> +	return r;
> +}
> +
>   static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)  {
>   	if (adev->is_atom_fw) {
> @@ -2730,16 +2769,20 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
>   
>   		if (!r) {
>   			dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
> -			r = amdgpu_resume(adev);
> +			r = amdgpu_resume_phase1(adev);
> +			if (r)
> +				goto out;
> +			r = amdgpu_ttm_recover_gart(adev);
> +			if (r)
> +				goto out;
> +			r = amdgpu_resume_phase2(adev);
> +			if (r)
> +				goto out;
>   		}
>   	}
> +out:
>   	if (!r) {
>   		amdgpu_irq_gpu_reset_resume_helper(adev);
> -		if (need_full_reset && amdgpu_need_backup(adev)) {
> -			r = amdgpu_ttm_recover_gart(adev);
> -			if (r)
> -				DRM_ERROR("gart recovery failed!!!\n");
> -		}
>   		r = amdgpu_ib_ring_tests(adev);
>   		if (r) {
>   			dev_err(adev->dev, "ib ring test failed (%d).\n", r);
> --
> 1.9.1
>
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