[PATCH 1/1] amdgpu: move asic id table to a separate file
Yuan, Xiaojie
Xiaojie.Yuan at amd.com
Thu May 11 10:51:00 UTC 2017
Hi Samuel,
Here's an off-by-one error:
+ id = asic_id_table + table_size -1;
should be:
+ id = asic_id_table + table_size;
Regards,
Xiaojie
________________________________
From: Li, Samuel
Sent: Thursday, May 11, 2017 4:56:55 AM
To: amd-gfx at lists.freedesktop.org
Cc: Yuan, Xiaojie; Li, Samuel
Subject: [PATCH 1/1] amdgpu: move asic id table to a separate file
From: Xiaojie Yuan <Xiaojie.Yuan at amd.com>
Change-Id: I12216da14910f5e2b0970bc1fafc2a20b0ef1ba9
Signed-off-by: Samuel Li <Samuel.Li at amd.com>
---
amdgpu/Makefile.am | 2 +
amdgpu/Makefile.sources | 2 +-
amdgpu/amdgpu_asic_id.c | 198 +++++++++++++++++++++++++++++++++++++++++++++++
amdgpu/amdgpu_asic_id.h | 165 ---------------------------------------
amdgpu/amdgpu_device.c | 28 +++++--
amdgpu/amdgpu_internal.h | 10 +++
6 files changed, 232 insertions(+), 173 deletions(-)
create mode 100644 amdgpu/amdgpu_asic_id.c
delete mode 100644 amdgpu/amdgpu_asic_id.h
diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
index cf7bc1b..ecf9e82 100644
--- a/amdgpu/Makefile.am
+++ b/amdgpu/Makefile.am
@@ -30,6 +30,8 @@ AM_CFLAGS = \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
+AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${datadir}/libdrm/amdgpu.ids\"
+
libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
libdrm_amdgpu_ladir = $(libdir)
libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined
diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources
index 487b9e0..bc3abaa 100644
--- a/amdgpu/Makefile.sources
+++ b/amdgpu/Makefile.sources
@@ -1,5 +1,5 @@
LIBDRM_AMDGPU_FILES := \
- amdgpu_asic_id.h \
+ amdgpu_asic_id.c \
amdgpu_bo.c \
amdgpu_cs.c \
amdgpu_device.c \
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
new file mode 100644
index 0000000..d50e21a
--- /dev/null
+++ b/amdgpu/amdgpu_asic_id.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright © 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
+{
+ char *buf;
+ char *s_did;
+ char *s_rid;
+ char *s_name;
+ char *endptr;
+ int r = 0;
+
+ buf = strdup(line);
+ if (!buf)
+ return -ENOMEM;
+
+ /* ignore empty line and commented line */
+ if (strlen(line) == 0 || line[0] == '#') {
+ r = -EAGAIN;
+ goto out;
+ }
+
+ /* device id */
+ s_did = strtok(buf, ",");
+ if (!s_did) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ id->did = strtol(s_did, &endptr, 16);
+ if (*endptr) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ /* revision id */
+ s_rid = strtok(NULL, ",");
+ if (!s_rid) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ id->rid = strtol(s_rid, &endptr, 16);
+ if (*endptr) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ /* marketing name */
+ s_name = strtok(NULL, ",");
+ if (!s_name) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ id->marketing_name = strdup(s_name);
+ if (id->marketing_name == NULL) {
+ r = -EINVAL;
+ goto out;
+ }
+
+out:
+ free(buf);
+
+ return r;
+}
+
+int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table)
+{
+ struct amdgpu_asic_id *asic_id_table;
+ struct amdgpu_asic_id *id;
+ FILE *fp;
+ char *line = NULL;
+ size_t len;
+ ssize_t n;
+ int line_num = 1;
+ size_t table_size = 0;
+ size_t table_max_size = 256;
+ int r = 0;
+
+ fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
+ if (!fp) {
+ fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE,
+ strerror(errno));
+ return -EINVAL;
+ }
+
+ asic_id_table = calloc(table_max_size, sizeof(struct amdgpu_asic_id));
+ if (!asic_id_table) {
+ r = -ENOMEM;
+ goto close;
+ }
+
+ /* 1st line is file version */
+ if ((n = getline(&line, &len, fp)) != -1) {
+ /* trim trailing newline */
+ if (line[n - 1] == '\n')
+ line[n - 1] = '\0';
+ printf("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line);
+ } else {
+ goto free;
+ }
+
+ while ((n = getline(&line, &len, fp)) != -1) {
+ id = asic_id_table + table_size;
+
+ /* trim trailing newline */
+ if (line[n - 1] == '\n')
+ line[n - 1] = '\0';
+
+ /*
+ * parse one line, its format looks like:
+ * 6617,C7,AMD Radeon R7 240 Series
+ */
+ r = parse_one_line(line, id);
+ if (r) {
+ if (r == -EAGAIN) {
+ line_num++;
+ continue;
+ }
+ fprintf(stderr, "Invalid format: %s: line %d: %s\n",
+ AMDGPU_ASIC_ID_TABLE, line_num, line);
+ goto free;
+ }
+
+ line_num++;
+ table_size++;
+
+ if (table_size >= table_max_size) {
+ /* double table size */
+ table_max_size *= 2;
+ asic_id_table = realloc(asic_id_table, table_max_size *
+ sizeof(struct amdgpu_asic_id));
+ if (!asic_id_table) {
+ r = -ENOMEM;
+ goto free;
+ }
+ }
+ }
+
+ /* end of table */
+ id = asic_id_table + table_size;
+ memset(id, 0, sizeof(struct amdgpu_asic_id));
+
+free:
+ free(line);
+
+ if (r && asic_id_table) {
+ while (table_size--) {
+ id = asic_id_table + table_size -1;
+ if (id->marketing_name != NULL)
+ free(id->marketing_name);
+ }
+ free(asic_id_table);
+ asic_id_table = NULL;
+ }
+close:
+ fclose(fp);
+
+ *p_asic_id_table = asic_id_table;
+
+ return r;
+}
diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h
deleted file mode 100644
index 3e7d736..0000000
--- a/amdgpu/amdgpu_asic_id.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright © 2016 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __AMDGPU_ASIC_ID_H__
-#define __AMDGPU_ASIC_ID_H__
-
-static struct amdgpu_asic_id_table_t {
- uint32_t did;
- uint32_t rid;
- const char *marketing_name;
-} const amdgpu_asic_id_table [] = {
- {0x6600, 0x0, "AMD Radeon HD 8600/8700M"},
- {0x6600, 0x81, "AMD Radeon R7 M370"},
- {0x6601, 0x0, "AMD Radeon HD 8500M/8700M"},
- {0x6604, 0x0, "AMD Radeon R7 M265 Series"},
- {0x6604, 0x81, "AMD Radeon R7 M350"},
- {0x6605, 0x0, "AMD Radeon R7 M260 Series"},
- {0x6605, 0x81, "AMD Radeon R7 M340"},
- {0x6606, 0x0, "AMD Radeon HD 8790M"},
- {0x6607, 0x0, "AMD Radeon HD8530M"},
- {0x6608, 0x0, "AMD FirePro W2100"},
- {0x6610, 0x0, "AMD Radeon HD 8600 Series"},
- {0x6610, 0x81, "AMD Radeon R7 350"},
- {0x6610, 0x83, "AMD Radeon R5 340"},
- {0x6611, 0x0, "AMD Radeon HD 8500 Series"},
- {0x6613, 0x0, "AMD Radeon HD 8500 series"},
- {0x6617, 0xC7, "AMD Radeon R7 240 Series"},
- {0x6640, 0x0, "AMD Radeon HD 8950"},
- {0x6640, 0x80, "AMD Radeon R9 M380"},
- {0x6646, 0x0, "AMD Radeon R9 M280X"},
- {0x6646, 0x80, "AMD Radeon R9 M470X"},
- {0x6647, 0x0, "AMD Radeon R9 M270X"},
- {0x6647, 0x80, "AMD Radeon R9 M380"},
- {0x6649, 0x0, "AMD FirePro W5100"},
- {0x6658, 0x0, "AMD Radeon R7 200 Series"},
- {0x665C, 0x0, "AMD Radeon HD 7700 Series"},
- {0x665D, 0x0, "AMD Radeon R7 200 Series"},
- {0x665F, 0x81, "AMD Radeon R7 300 Series"},
- {0x6660, 0x0, "AMD Radeon HD 8600M Series"},
- {0x6660, 0x81, "AMD Radeon R5 M335"},
- {0x6660, 0x83, "AMD Radeon R5 M330"},
- {0x6663, 0x0, "AMD Radeon HD 8500M Series"},
- {0x6663, 0x83, "AMD Radeon R5 M320"},
- {0x6664, 0x0, "AMD Radeon R5 M200 Series"},
- {0x6665, 0x0, "AMD Radeon R5 M200 Series"},
- {0x6665, 0x83, "AMD Radeon R5 M320"},
- {0x6667, 0x0, "AMD Radeon R5 M200 Series"},
- {0x666F, 0x0, "AMD Radeon HD 8500M"},
- {0x6780, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"},
- {0x678A, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"},
- {0x6798, 0x0, "AMD Radeon HD 7900 Series"},
- {0x679A, 0x0, "AMD Radeon HD 7900 Series"},
- {0x679B, 0x0, "AMD Radeon HD 7900 Series"},
- {0x679E, 0x0, "AMD Radeon HD 7800 Series"},
- {0x67A0, 0x0, "HAWAII XTGL (67A0)"},
- {0x67A1, 0x0, "HAWAII GL40 (67A1)"},
- {0x67B0, 0x0, "AMD Radeon R9 200 Series"},
- {0x67B0, 0x80, "AMD Radeon R9 390 Series"},
- {0x67B1, 0x0, "AMD Radeon R9 200 Series"},
- {0x67B1, 0x80, "AMD Radeon R9 390 Series"},
- {0x67B9, 0x0, "AMD Radeon R9 200 Series"},
- {0x67DF, 0xC4, "AMD Radeon RX 480 Graphics"},
- {0x67DF, 0xC5, "AMD Radeon RX 470 Graphics"},
- {0x67DF, 0xC7, "AMD Radeon RX 480 Graphics"},
- {0x67DF, 0xCF, "AMD Radeon RX 470 Graphics"},
- {0x67C4, 0x00, "AMD Radeon Pro WX 7100 Graphics"},
- {0x67C7, 0x00, "AMD Radeon Pro WX 5100 Graphics"},
- {0x67C0, 0x00, "AMD Radeon Pro WX 7100 Graphics"},
- {0x67E0, 0x00, "AMD Radeon Pro WX Series Graphics"},
- {0x67E3, 0x00, "AMD Radeon Pro WX 4100 Graphics"},
- {0x67E8, 0x00, "AMD Radeon Pro WX Series Graphics"},
- {0x67E8, 0x01, "AMD Radeon Pro WX Series Graphics"},
- {0x67E8, 0x80, "AMD Radeon E9260 Graphics"},
- {0x67EB, 0x00, "AMD Radeon Pro WX Series Graphics"},
- {0x67EF, 0xC0, "AMD Radeon RX Graphics"},
- {0x67EF, 0xC1, "AMD Radeon RX 460 Graphics"},
- {0x67EF, 0xC5, "AMD Radeon RX 460 Graphics"},
- {0x67EF, 0xC7, "AMD Radeon RX Graphics"},
- {0x67EF, 0xCF, "AMD Radeon RX 460 Graphics"},
- {0x67EF, 0xEF, "AMD Radeon RX Graphics"},
- {0x67FF, 0xC0, "AMD Radeon RX Graphics"},
- {0x67FF, 0xC1, "AMD Radeon RX Graphics"},
- {0x6800, 0x0, "AMD Radeon HD 7970M"},
- {0x6801, 0x0, "AMD Radeon(TM) HD8970M"},
- {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"},
- {0x6809, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"},
- {0x6810, 0x0, "AMD Radeon(TM) HD 8800 Series"},
- {0x6810, 0x81, "AMD Radeon R7 370 Series"},
- {0x6811, 0x0, "AMD Radeon(TM) HD8800 Series"},
- {0x6811, 0x81, "AMD Radeon R7 300 Series"},
- {0x6818, 0x0, "AMD Radeon HD 7800 Series"},
- {0x6819, 0x0, "AMD Radeon HD 7800 Series"},
- {0x6820, 0x0, "AMD Radeon HD 8800M Series"},
- {0x6820, 0x81, "AMD Radeon R9 M375"},
- {0x6820, 0x83, "AMD Radeon R9 M375X"},
- {0x6821, 0x0, "AMD Radeon HD 8800M Series"},
- {0x6821, 0x87, "AMD Radeon R7 M380"},
- {0x6821, 0x83, "AMD Radeon R9 M370X"},
- {0x6822, 0x0, "AMD Radeon E8860"},
- {0x6823, 0x0, "AMD Radeon HD 8800M Series"},
- {0x6825, 0x0, "AMD Radeon HD 7800M Series"},
- {0x6827, 0x0, "AMD Radeon HD 7800M Series"},
- {0x6828, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"},
- {0x682B, 0x0, "AMD Radeon HD 8800M Series"},
- {0x682B, 0x87, "AMD Radeon R9 M360"},
- {0x682C, 0x0, "AMD FirePro W4100"},
- {0x682D, 0x0, "AMD Radeon HD 7700M Series"},
- {0x682F, 0x0, "AMD Radeon HD 7700M Series"},
- {0x6835, 0x0, "AMD Radeon R7 Series / HD 9000 Series"},
- {0x6837, 0x0, "AMD Radeon HD7700 Series"},
- {0x683D, 0x0, "AMD Radeon HD 7700 Series"},
- {0x683F, 0x0, "AMD Radeon HD 7700 Series"},
- {0x6900, 0x0, "AMD Radeon R7 M260"},
- {0x6900, 0x81, "AMD Radeon R7 M360"},
- {0x6900, 0x83, "AMD Radeon R7 M340"},
- {0x6901, 0x0, "AMD Radeon R5 M255"},
- {0x6907, 0x0, "AMD Radeon R5 M255"},
- {0x6907, 0x87, "AMD Radeon R5 M315"},
- {0x6920, 0x0, "AMD Radeon R9 M395X"},
- {0x6920, 0x1, "AMD Radeon R9 M390X"},
- {0x6921, 0x0, "AMD Radeon R9 M295X"},
- {0x6929, 0x0, "AMD FirePro S7150"},
- {0x692B, 0x0, "AMD FirePro W7100"},
- {0x6938, 0x0, "AMD Radeon R9 200 Series"},
- {0x6938, 0xF0, "AMD Radeon R9 200 Series"},
- {0x6938, 0xF1, "AMD Radeon R9 380 Series"},
- {0x6939, 0xF0, "AMD Radeon R9 200 Series"},
- {0x6939, 0x0, "AMD Radeon R9 200 Series"},
- {0x6939, 0xF1, "AMD Radeon R9 380 Series"},
- {0x7300, 0xC8, "AMD Radeon R9 Fury Series"},
- {0x7300, 0xCB, "AMD Radeon R9 Fury Series"},
- {0x7300, 0xCA, "AMD Radeon R9 Fury Series"},
- {0x9874, 0xC4, "AMD Radeon R7 Graphics"},
- {0x9874, 0xC5, "AMD Radeon R6 Graphics"},
- {0x9874, 0xC6, "AMD Radeon R6 Graphics"},
- {0x9874, 0xC7, "AMD Radeon R5 Graphics"},
- {0x9874, 0x81, "AMD Radeon R6 Graphics"},
- {0x9874, 0x87, "AMD Radeon R5 Graphics"},
- {0x9874, 0x85, "AMD Radeon R6 Graphics"},
- {0x9874, 0x84, "AMD Radeon R7 Graphics"},
-
- {0x0000, 0x0, "\0"},
-};
-#endif
diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index f473d2d..9d08744 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -44,7 +44,6 @@
#include "amdgpu_internal.h"
#include "util_hash_table.h"
#include "util_math.h"
-#include "amdgpu_asic_id.h"
#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
#define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
@@ -131,6 +130,7 @@ static int amdgpu_get_auth(int fd, int *auth)
static void amdgpu_device_free_internal(amdgpu_device_handle dev)
{
+ const struct amdgpu_asic_id *id;
amdgpu_vamgr_deinit(&dev->vamgr_32);
amdgpu_vamgr_deinit(&dev->vamgr);
util_hash_table_destroy(dev->bo_flink_names);
@@ -140,6 +140,13 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev)
close(dev->fd);
if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
close(dev->flink_fd);
+ if (dev->asic_ids) {
+ for (id = dev->asic_ids; id->did; id++) {
+ if (id->marketing_name != NULL)
+ free(id->marketing_name);
+ }
+ free(dev->asic_ids);
+ }
free(dev);
}
@@ -267,6 +274,11 @@ int amdgpu_device_initialize(int fd,
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
dev->dev_info.virtual_address_alignment);
+ r = amdgpu_parse_asic_ids(&dev->asic_ids);
+ if (r)
+ fprintf(stderr, "%s: Can not parse asic ids, 0x%x.",
+ __func__, r);
+
*major_version = dev->major_version;
*minor_version = dev->minor_version;
*device_handle = dev;
@@ -297,13 +309,15 @@ int amdgpu_device_deinitialize(amdgpu_device_handle dev)
const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
{
- const struct amdgpu_asic_id_table_t *t = amdgpu_asic_id_table;
+ const struct amdgpu_asic_id *id;
+
+ if (!dev->asic_ids)
+ return NULL;
- while (t->did) {
- if ((t->did == dev->info.asic_id) &&
- (t->rid == dev->info.pci_rev_id))
- return t->marketing_name;
- t++;
+ for (id = dev->asic_ids; id->did; id++) {
+ if ((id->did == dev->info.asic_id) &&
+ (id->rid == dev->info.pci_rev_id))
+ return id->marketing_name;
}
return NULL;
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index cf119a5..9d11bea 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -69,6 +69,12 @@ struct amdgpu_va {
struct amdgpu_bo_va_mgr *vamgr;
};
+struct amdgpu_asic_id {
+ uint32_t did;
+ uint32_t rid;
+ char *marketing_name;
+};
+
struct amdgpu_device {
atomic_t refcount;
int fd;
@@ -76,6 +82,8 @@ struct amdgpu_device {
unsigned major_version;
unsigned minor_version;
+ /** Lookup table of asic device id, revision id and marketing name */
+ struct amdgpu_asic_id *asic_ids;
/** List of buffer handles. Protected by bo_table_mutex. */
struct util_hash_table *bo_handles;
/** List of buffer GEM flink names. Protected by bo_table_mutex. */
@@ -149,6 +157,8 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size);
+drm_private int amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids);
+
drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
--
2.7.4
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