[PATCH 1/4] drm/amd/amdgpu: Use 32/64-bit types in uvd42

[Tom St Denis]

Swap uNN for uintNN_t.

Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 8ab0f78794a5..eccf4c467fe1 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -254,10 +254,10 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
 	struct amdgpu_ring *ring = &adev->uvd.ring;
 	uint32_t rb_bufsz;
 	int i, j, r;
-	u32 tmp;
+	uint32_t tmp;
 	/* disable byte swapping */
-	u32 lmi_swap_cntl = 0;
-	u32 mp_swap_cntl = 0;
+	uint32_t lmi_swap_cntl = 0;
+	uint32_t mp_swap_cntl = 0;
 
 	/* set uvd busy */
 	WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
@@ -441,7 +441,7 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
  *
  * Write a fence and a trap command to the ring.
  */
-static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq,
 				     unsigned flags)
 {
 	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
@@ -594,7 +594,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
 				 bool enable)
 {
-	u32 orig, data;
+	uint32_t orig, data;
 
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
 		data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
@@ -620,7 +620,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
 			     bool sw_mode)
 {
-	u32 tmp, tmp2;
+	uint32_t tmp, tmp2;
 
 	WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
 
-- 
2.12.0