[PATCH 15/31] drm/amd/display: Refactor use_lut() from dce110 to dce

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li at amd.com>

use_lut() checks if the input surface's pixel format is compatible with
a 256 entry LUT. This function can be used across different versions and
not just dce11.

Change-Id: Ia2813007c91f39939e0ceef65e2f68af0a5e235c
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c          | 12 ++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h          |  2 ++
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 ++---------------
 3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 34c18712970c..cc3178acfc54 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -191,3 +191,15 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
 		       clk_src->id, tg_inst);
 	}
 }
+
+/* Only use LUT for 8 bit formats */
+bool dce_use_lut(const struct core_surface *surface)
+{
+	switch (surface->public.format) {
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+		return true;
+	default:
+		return false;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index dd13f47b6446..112f9c85c142 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -256,4 +256,6 @@ void dce_clock_gating_power_up(struct dce_hwseq *hws,
 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
 		struct clock_source *clk_src,
 		unsigned int tg_inst);
+
+bool dce_use_lut(const struct core_surface *surface);
 #endif   /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 20ad1cb263db..65c691569eb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -28,10 +28,10 @@
 #include "core_types.h"
 #include "core_status.h"
 #include "resource.h"
-#include "hw_sequencer.h"
 #include "dm_helpers.h"
 #include "dce110_hw_sequencer.h"
 #include "dce110_timing_generator.h"
+#include "dce/dce_hwseq.h"
 
 #include "bios/bios_parser_helper.h"
 #include "timing_generator.h"
@@ -233,19 +233,6 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 	}
 }
 
-
-/* Only use LUT for 8 bit formats */
-static bool use_lut(const struct core_surface *surface)
-{
-	switch (surface->public.format) {
-	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-		return true;
-	default:
-		return false;
-	}
-}
-
 static bool dce110_set_input_transfer_func(
 	struct pipe_ctx *pipe_ctx,
 	const struct core_surface *surface)
@@ -264,7 +251,7 @@ static bool dce110_set_input_transfer_func(
 	build_prescale_params(&prescale_params, surface);
 	ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 
-	if (surface->public.gamma_correction && use_lut(surface))
+	if (surface->public.gamma_correction && dce_use_lut(surface))
 	    ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction);
 
 	if (tf == NULL) {
-- 
2.11.0