[PATCH 22/31] drm/amd/display: Clean up indentation in dce120_tg_set_blank()

[Harry Wentland]

From: Tom St Denis <tom.stdenis at amd.com>

Change-Id: Ib2f7b1a4c55033028b88351e8d278cfb77b71c4d
Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland at amd.com>
---
 .../drm/amd/display/dc/dce120/dce120_timing_generator.c  | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 1e2843e5d97e..c208196864ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -768,17 +768,11 @@ void dce120_tg_set_blank(struct timing_generator *tg,
 		CRTC0_CRTC_DOUBLE_BUFFER_CONTROL,
 		CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
 
-	if (enable_blanking) {
-		CRTC_REG_SET(
-			CRTC0_CRTC_BLANK_CONTROL,
-			CRTC_BLANK_DATA_EN, 1);
-
-	} else
-		dm_write_reg_soc15(
-			tg->ctx,
-			mmCRTC0_CRTC_BLANK_CONTROL,
-			tg110->offsets.crtc,
-			0);
+	if (enable_blanking)
+		CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
+	else
+		dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
+			tg110->offsets.crtc, 0);
 }
 
 bool dce120_tg_validate_timing(struct timing_generator *tg,
-- 
2.11.0