[PATCH] drm/amdgpu: update golden settings

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Ken Wang
> Sent: Wednesday, May 17, 2017 5:08 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Wang, Ken
> Subject: [PATCH] drm/amdgpu: update golden settings
> 
> Change-Id: Ifcc39748c36273fa764cd2641d4b44405dbf59a5
> Signed-off-by: Ken Wang <Qingqing.Wang at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 39ae97b..de35de2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -86,14 +86,27 @@ static const struct amdgpu_gds_reg_offset
> amdgpu_gds_reg_offset[] =
> 
>  static const u32 golden_settings_gc_9_0[] =
>  {
> -	SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff,
> 0x00000400,
> +	SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000,
> 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000,
> 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000,
> 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
> +	SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f,
> 0x00000000,
> +	SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000,
> 0x08000080,
>  	SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3),
> 0x00000003, 0x82400024,
>  	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff,
> 0x00000001,
>  	SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE),
> 0x0000ff0f, 0x00000000,
> +	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0),
> 0x08000000, 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1),
> 0x08000000, 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2),
> 0x08000000, 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL),
> 0x08000000, 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000,
> 0x08000080,
> +	SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f,
> 0x01000107,
>  	SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef,
> 0x010b0000,
>  	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff,
> 0x4a2c0e68,
>  	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff,
> 0xb5d3f197,
> -	SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID),
> 0x00000fff, 0x000003ff
> +	SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION),
> 0x3fff3af3, 0x19200000,
> +	SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID),
> 0x00000fff, 0x000003ff,
> +	SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000,
> 0x08000080
>  };
> 
>  static const u32 golden_settings_gc_9_0_vg10[] =
> @@ -104,8 +117,7 @@ static const u32 golden_settings_gc_9_0_vg10[] =
>  	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ),
> 0xffff77ff, 0x2a114042,
>  	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000,
> 0x00048000,
>  	SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000,
> 0x00020000,
> -	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
> -	SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f,
> 0x00000007
> +	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
>  };
> 
>  #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
> --
> 2.7.4
> 
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