[PATCH 1/6] drm/amd/powerplay: initialize rv vq table

Hawking Zhang Hawking.Zhang at amd.com
Wed May 24 11:13:42 UTC 2017


Change-Id: I64696e3b5418bcdb24a2c359677506d87769afaf
Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 47 +++++++++++++++++---------
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h      | 18 +++++++++-
 2 files changed, 48 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 631ef82..26906c3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -45,10 +45,28 @@
 
 static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Cz_Magic;
 
-struct phm_vq_budgeting_record rv_vqtable[] = {
-	/* _TBD
-	 * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */
-	{ 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 },
+struct phm_vq_budgeting_settings RV_VQTable[] =
+{
+	/* CUs, SSP low, SSP High, Display Configuration, AWD/non-AWD,
+	 * Sustainable GFXCLK, Sustainable FCLK, Sustainable CUs,
+         * unused, unused, unused */
+	{ 11, 30, 60, VQ_DisplayConfig_NoneAWD,  80000, 160000, 11, 0, 0, 0 },
+	{ 11, 30, 60, VQ_DisplayConfig_AWD,      80000, 160000, 11, 0, 0, 0 },
+
+	{  8, 30, 60, VQ_DisplayConfig_NoneAWD, 100000, 160000,  8, 0, 0, 0 },
+	{  8, 30, 60, VQ_DisplayConfig_AWD,     100000, 160000,  8, 0, 0, 0 },
+
+	{ 10, 12, 30, VQ_DisplayConfig_NoneAWD,  40000, 120000, 10, 0, 0, 0 },
+	{ 10, 12, 30, VQ_DisplayConfig_AWD,      40000, 120000, 10, 0, 0, 0 },
+
+	{  8, 12, 30, VQ_DisplayConfig_NoneAWD,  45000, 120000,  8, 0, 0, 0 },
+	{  8, 12, 30, VQ_DisplayConfig_AWD,      45000, 120000,  8, 0, 0, 0 },
+
+	{  6, 12, 30, VQ_DisplayConfig_NoneAWD,  45000, 120000,  6, 0, 0, 0 },
+	{  6, 12, 30, VQ_DisplayConfig_AWD,      45000, 120000,  6, 0, 0, 0 },
+
+	{  3, 12, 30, VQ_DisplayConfig_NoneAWD,  45000, 120000,  3, 0, 0, 0 },
+	{  3, 12, 30, VQ_DisplayConfig_AWD,      45000, 120000,  3, 0, 0, 0 },
 };
 
 static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
@@ -72,13 +90,13 @@ static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
 {
 	uint32_t table_size, i;
 	struct phm_vq_budgeting_table *ptable;
-	uint32_t num_entries = ARRAY_SIZE(rv_vqtable);
+	uint32_t num_entries = sizeof(RV_VQTable)/sizeof(*RV_VQTable);
 
 	if (hwmgr->dyn_state.vq_budgeting_table != NULL)
 		return 0;
 
 	table_size = sizeof(struct phm_vq_budgeting_table) +
-			sizeof(struct phm_vq_budgeting_record) * (num_entries - 1);
+		sizeof(struct phm_vq_budgeting_record) * (num_entries - 1);
 
 	ptable = kzalloc(table_size, GFP_KERNEL);
 	if (NULL == ptable)
@@ -87,16 +105,13 @@ static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
 	ptable->numEntries = (uint8_t) num_entries;
 
 	for (i = 0; i < ptable->numEntries; i++) {
-		ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs;
-		ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow;
-		ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh;
-		ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow;
-		ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh;
-		ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig;
-		ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk;
-		ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk;
-		ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk;
-		ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs;
+		ptable->settings[i].ulSetting1 = RV_VQTable[i].ulSetting1;
+		ptable->settings[i].ulSetting2 = RV_VQTable[i].ulSetting2;
+		ptable->settings[i].ulSetting3 = RV_VQTable[i].ulSetting3;
+		ptable->settings[i].ulSetting4 = RV_VQTable[i].ulSetting4;
+		ptable->settings[i].ulSetting5 = RV_VQTable[i].ulSetting5;
+		ptable->settings[i].ulSetting6 = RV_VQTable[i].ulSetting6;
+		ptable->settings[i].ulSetting7 = RV_VQTable[i].ulSetting7;
 	}
 
 	hwmgr->dyn_state.vq_budgeting_table = ptable;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 35cb26f..7779600 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -519,9 +519,25 @@ struct phm_vq_budgeting_record {
 	uint32_t ulSustainableCUs;
 };
 
+struct phm_vq_budgeting_settings {
+	uint32_t ulSetting1;	/* RV: CUs */
+	uint32_t ulSetting2;	/* RV: SustainableSOCPowerLimitLow in W */
+	uint32_t ulSetting3;	/* RV: SustainableSOCPowerLimitHigh in W */
+	uint8_t ulSetting4;	/* RV: DispConfig */
+	uint32_t ulSetting5;	/* RV: Sustainable GFXCLK in 10KHz */
+	uint32_t ulSetting6;	/* RV: Sustainable FCLK in 10KHz */
+	uint32_t ulSetting7;	/* RV: Sustainable CUs */
+	uint32_t ulSetting8;	/* unused */
+	uint32_t ulSetting9;	/* unused */
+	uint32_t ulSetting10;	/* unused */
+};
+
 struct phm_vq_budgeting_table {
 	uint8_t numEntries;
-	struct phm_vq_budgeting_record entries[1];
+	union {
+		struct phm_vq_budgeting_record   entries[1];
+		struct phm_vq_budgeting_settings settings[1];
+	};
 };
 
 struct phm_clock_and_voltage_limits {
-- 
2.7.4



More information about the amd-gfx mailing list