[PATCH 1/4] drm/amd/powerplay: hardcode temp range to 0-89 for vega10.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 1/4] drm/amd/powerplay: hardcode temp range to 0-89 for
> vega10.
> 
> clean up code in vega10_thermal.c

Please split this into 2 patches, one to clean up the code, one to make the change for the temp range.  For the temp range change, would it be better to change the current define to 89 rather than just hardcoding it as a magic number?

Alex

> 
> Change-Id: I2eb0b6c9afa4fa23d31b4dfed317689623fcbcda
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c   | 49 ++++++++-----
> ---------
>  1 file changed, 17 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> index 7bb4e46..1bc39ec 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> @@ -144,21 +144,13 @@ int vega10_fan_ctrl_set_static_mode(struct
> pp_hwmgr *hwmgr, uint32_t mode)
>  				(cgs_read_register(hwmgr->device, reg) &
>  				CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
> >>
> 
> 	CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
> -		hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
> -				CG_FDO_CTRL2__TMIN_MASK) >>
> -				CG_FDO_CTRL2__TMIN__SHIFT;
>  		hwmgr->fan_ctrl_is_in_default_mode = false;
>  	}
> 
>  	cgs_write_register(hwmgr->device, reg,
>  			(cgs_read_register(hwmgr->device, reg) &
> -			~CG_FDO_CTRL2__TMIN_MASK) |
> -			(0 << CG_FDO_CTRL2__TMIN__SHIFT));
> -	cgs_write_register(hwmgr->device, reg,
> -			(cgs_read_register(hwmgr->device, reg) &
>  			~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
>  			(mode <<
> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
> -
>  	return 0;
>  }
> 
> @@ -170,20 +162,18 @@ int vega10_fan_ctrl_set_static_mode(struct
> pp_hwmgr *hwmgr, uint32_t mode)
>  int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
>  {
>  	uint32_t reg;
> +	uint32_t ctrl;
> 
>  	reg = soc15_get_register_offset(THM_HWID, 0,
>  			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
> 
>  	if (!hwmgr->fan_ctrl_is_in_default_mode) {
> -		cgs_write_register(hwmgr->device, reg,
> -				(cgs_read_register(hwmgr->device, reg) &
> -
> 	~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
> -				(hwmgr->fan_ctrl_default_mode <<
> -
> 	CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
> -		cgs_write_register(hwmgr->device, reg,
> -				(cgs_read_register(hwmgr->device, reg) &
> -				~CG_FDO_CTRL2__TMIN_MASK) |
> -				(hwmgr->tmin <<
> CG_FDO_CTRL2__TMIN__SHIFT));
> +		ctrl = cgs_read_register(hwmgr->device, reg);
> +		ctrl = ctrl & (~(CG_FDO_CTRL2__FDO_PWM_MODE_MASK));
> +		ctrl = ctrl | (hwmgr->fan_ctrl_default_mode <<
> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
> +		ctrl = ctrl & (~(CG_FDO_CTRL2__TMIN_MASK));
> +		ctrl = ctrl | (hwmgr->tmin <<
> CG_FDO_CTRL2__TMIN__SHIFT);
> +		cgs_write_register(hwmgr->device, reg, ctrl);
>  		hwmgr->fan_ctrl_is_in_default_mode = true;
>  	}
> 
> @@ -325,9 +315,9 @@ int
> vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
>  				FDO_PWM_MODE_STATIC);
>  		if (!result)
>  			result =
> vega10_fan_ctrl_start_smc_fan_control(hwmgr);
> -	} else
> +	} else {
>  		result = vega10_fan_ctrl_set_default_mode(hwmgr);
> -
> +	}
>  	return result;
>  }
> 
> @@ -404,15 +394,10 @@ static int
> vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
>  {
>  	uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
>  			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
> -	uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
> +	uint32_t high = 89 *
>  			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
>  	uint32_t val, reg;
> 
> -	if (low < range->min)
> -		low = range->min;
> -	if (high > range->max)
> -		high = range->max;
> -
>  	if (low > high)
>  		return -EINVAL;
> 
> @@ -420,7 +405,6 @@ static int
> vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
>  			mmTHM_THERMAL_INT_CTRL_BASE_IDX,
> mmTHM_THERMAL_INT_CTRL);
> 
>  	val = cgs_read_register(hwmgr->device, reg);
> -
>  	val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
>  	val |=  (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
> 
> @@ -450,24 +434,25 @@ static int
> vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
>  static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
>  {
>  	uint32_t reg;
> +	uint32_t tmp;
> 
>  	if (hwmgr-
> >thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
>  		reg = soc15_get_register_offset(THM_HWID, 0,
>  				mmCG_TACH_CTRL_BASE_IDX,
> mmCG_TACH_CTRL);
> -		cgs_write_register(hwmgr->device, reg,
> -				(cgs_read_register(hwmgr->device, reg) &
> +		tmp = (cgs_read_register(hwmgr->device, reg) &
>  				~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
>  				((hwmgr->thermal_controller.fanInfo.
>  				ucTachometerPulsesPerRevolution - 1) <<
> -				CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
> +				CG_TACH_CTRL__EDGE_PER_REV__SHIFT);
> +		cgs_write_register(hwmgr->device, reg, tmp);
>  	}
> 
>  	reg = soc15_get_register_offset(THM_HWID, 0,
>  			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
> -	cgs_write_register(hwmgr->device, reg,
> -			(cgs_read_register(hwmgr->device, reg) &
> +	tmp = (cgs_read_register(hwmgr->device, reg) &
>  			~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK)
> |
> -			(0x28 <<
> CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
> +			(0x28 <<
> CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT);
> +	cgs_write_register(hwmgr->device, reg, tmp);
> 
>  	return 0;
>  }
> --
> 1.9.1
> 
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